Inductive properties of high-performance power distribution grids

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

分形树电源网格对芯片电源完整性的改善

基于叶脉网格结构,用分形理论及Murray定律确定网格几何尺寸。设计树网络体积与电阻间存在幂指数0.22的相似规律关系。设计的分形电源网格,改善了电阻、电感压降。本设计中芯片上模拟、数字电源/地线不共用,分别由主脉两侧的第二级脉供电,从而有效隔离了噪声。     

Artificial Neural Network Models for the Crossover Discontinuities in Stripline Circuits

Crossover discontinuities between two adjacent orthogonal signal layers often appear in many stripline circuits, such as the multilayer microwave monolithic ICs and the interconnect systems in high-speed digital circuits. In this paper , a multilayer perceptron neural network(MLPNN) is used to model the electrical properties of the crossover discontinuities in stripline circuits. The MLPNN is electromagnetically developed with a set of training data that are produced by the full-wave finite-difference time-domain method. The full-factor design of experiments is used to determine the size of the training data.     

Frequency Characteristics of High Speed Power Distribution Grids

The variation of inductance with frequency in high performance power distribution grids is discussed in this paper. The impedance characteristics of the power grid need to be well understood for the design of efficient and robust high performance power distribution grids. The physical mechanisms underlying the dependence of inductance on frequency are discussed. The variation of inductance with frequency in three types of power grids is analyzed in terms of these mechanisms.The inductance of power distribution grids decreases with signal frequency. The decrease in inductance in non-interdigitated grids is primarily due to current redistribution in multiple forward and return current paths. In interdigitated grids, the variation of inductance with frequency is fairly small, typically less than 10% because both proximity and multi-path current redistribution effects are minimal. In paired grids, the relative decrease in inductance with frequency is larger as compared to interdigitated grids. This behavior is due to significant proximity effects. The smaller the separation between the power and ground lines and the wider the lines, the more significant proximity effects become and the greater the relative decrease in inductance with frequency.     

Power distribution techniques for VLSI circuits

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.     

Optimal n-tier multilevel interconnect architectures for gigascaleintegration (GSI)

A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell     

Design and Fabrication of Stretchable Multilayer Self-Aligned Interconnects for Flexible Electronics and Large-Area Sensor Arrays Using Excimer Laser Photoablation

Stretchable interconnects are fabricated on polymer substrates using metal patterns both as functional interconnect layers and as in situ masks for excimer laser photoablation. Single-layer and multilayer interconnects of various designs (rectilinear and “meandering”) have been fabricated, and certain “meandering” interconnect designs can be stretched up to 50% uniaxially while maintaining good electrical conductivity and structural integrity. This approach eliminates masks and microfabrication processing steps as compared to traditional fabrication approaches. Furthermore, this technology is scalable for large-area sensor arrays and electronic circuits, adaptable for a variety of materials and interconnects designs, and compatible with MEMS-based capacitive sensor technology.      

Magnetic-Multilayered Interconnects Featuring Skin Effect Suppression

A novel concept for a high-frequency, low-loss interconnect with significant skin effect suppression over a wide frequency band is presented. The concept is based on a multilayer comprising thin magnetic (Ni₈₀Fe₂₀) and metal (Cu) layers. The negative permeability of the magnetic layers leads to a near-cancellation of the overall permeability of the multilayer stack. This results in a significant increase of skin depth and thus, a more uniform distribution of the current density and a dramatic reduction of loss within a certain frequency range. Coplanar waveguides built using the multilayer technology show more than 50% loss reduction at 14 GHz compared to their thick Cu-based counterparts.     

Power characteristics of inductive interconnect

The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.     

Modeling of Multilayer Suspended Microstrip Line and its Discontinuities on CMOS Grade Silicon Substrate for Millimeter Wave Integrated Circuit Applications

Transmission line parameters such as characteristic impedance Z₀, effective dielectric constant ε_eff, attenuation constant α of suspended microstrip line on multilayer low resistively silicon substrate are investigated using full wave FEM simulator HFSS. Effect of variation in the thickness of Si₃N_4, polyimide and metal layers on attenuation are studied. Due to suspended nature, significant reduction in transmission loss is observed in the simulation at 60 GHz frequency. Discontinuities such as open end, gap and step in width of strip conductor are analyzed to extract their lumped equivalent circuits which can be used in the design of integrated circuits.     

Exploiting CMOS reverse interconnect scaling in multigigahertzamplifier and oscillator design

The increasing number of interconnect layers that are needed in a CMOS process to meet the routing and power requirements of large digital circuits also yield significant advantages for analog applications. The reverse thickness scaling of the top metal layer can be exploited in the design of low-loss transmission lines. Coplanar transmission lines in the top metal layers take advantage of a low metal resistance and a large separation from the heavily doped silicon substrate. They are therefore fully compatible with current and future CMOS process technologies. To investigate the feasibility of extending CMOS designs beyond 10 GHz, a wide range of coplanar transmission lines are characterized. The effect of the substrate resistivity on coplanar wave propagation is explained. After achieving a record loss of 0.3 dB/mm at 50 GHz, coplanar lines are used in the design of distributed amplifiers and oscillators. They are the first to achieve higher than 10 GHz operating frequencies in a conventional CMOS technology     

高速集成电路电源网络的频率特性分析

提出了用一种简单模型计算随频率变化的电感。由于稠密的部分电感矩阵使得方程求解非常困难，采用二次求逆的方法对其进行处理。采用频变电感的计算方法，分析了三种类型电源网络的电感随频率变化的特性。由计算结果可知，网络的回路电感随信号频率的升高呈下降趋势，且成对分布的电源网络的回路电感最小。这为电源网络的设计和同步开关噪声的分析提供了一定的依据。     

Validity and Accuracy of Equivalent Circuit Models of Passive Inductive Meshes. Definition of a Novel Model for 2D Grids

Accuracy of equivalent circuit models of periodic grids is investigated in amplitude and phase in the visible region. The grids studied here are one-dimensional (1D) and two-dimensional (2D) inductive thin metal meshes. They are located in free space and are illuminated by a plane wave under normal incidence. The range of validity and the accuracy of conventional circuit models are defined by comparison with rigorous results obtained with the Finite-Difference Time-Domain (FDTD) method. In particular, it is shown that electrical models of 1D grids are accurate, whereas equivalent circuits of 2D grids should be used very cautiously. Then, a new formulation is proposed to overcome this major drawback. In the non-diffraction region, the agreement between our model and the FDTD results is within 2% for the power reflectivity and 1° for the phase over a very wide range of strip widths.     

High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors

High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.     

多层金属栅网混合结构吸波特性分析

文中采用传输矩阵理论和二端口级联网络分析了多层金属栅网混合结构的吸波特性,通过将多层金属栅网与多层介质阻抗匹配,在介质厚度不变的情况下,明显提高了混合结构的吸收峰值;同时,通过调整每层金属栅网的半径、间距,可调整混合结构吸收峰值位置,给出了典型混合结构的仿真计算结果.结果表明,混合结构吸收峰值可提高6 dB以上,在保证吸收效果的前提下,调整了吸收峰值的位置,可根据要求用于设计不同频段的吸波材料.     

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, circuit design is burdened to ldquohiderdquo more of the problems intrinsic to deeply scaled devices. How this is being accomplished is the subject of this paper. We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices. We discuss the unique problems posed by nanoscale lithography and the role of geometrically regular circuits as one promising solution. Finally, we look at recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.     

Progress in the methodologies for the electrical modeling ofinterconnects and electronic packages

The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance- and/or portability-driven, multifunctional ULSI systems     

Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs

We measured and demonstrated the great advantages of embedded film capacitors in reducing power/ground inductive impedance and the suppression of SSN at frequencies up to 3 GHz for high-performance multilayer packages and PCBs. Eight-layer test PCBs were fabricated, and their inductive power/ground network impedances were measured as a function of film thickness, via distribution, and combined use with discrete decoupling capacitors, using a two-port self-impedance measurement method. This successfully demonstrated that the power/ground inductive impedance was reduced from 270 pH to 106 pH simply by using an embedded film capacitor instead of 16 discrete decoupling capacitors.     

Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI)

The supply voltage decrease and power density increase of future GSI chips demand accurate models for the IR-drop. Compact physical IR-drop models of on-chip power/ground distribution networks are derived for two generic types of packages. In the early stages of design, these models enable accurate estimates of all required power/ground grid interconnect dimensions and chip pad counts that are needed for power distribution. The models also quantify the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution and therefore enable rigorous chip/package co-design. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the flip-chip package, respectively.