Inductive properties of high-performance power distribution grids

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.     

集成电路低功耗设计方法

针对当前集成电路低功耗的需求,对当前几种常用的低功耗设计方法和技术进行探讨,包括算法优化、工艺优化、版图优化、门级优化等,从而为当前继承电路优化提供借鉴参考。     

集成电路低功耗设计方法

信息化的社会发展无法离开电子产品的不断进步,而其对其低功耗的设计要求正在不断增强.但当前电子产品的功能质量在提高的同时,其功耗设计却没能跟上设计的要求,一直处于上升趋势,这将对电子产品性能的提高产生一定的影响.一款经久耐用、性能强的电子产品必须具备水平相当的低功耗设计方式.本文主要探讨了集成电路的低功耗设计方法,以作为相关参考.     

Gate-level power and current simulation of CMOS integrated circuits

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser     

Base diffusion isolated transistors for low power integrated circuits

Base diffusion isolated transistors (BDI) designed for low power, nonsaturating, integrated circuits have been fabricated. Buried collectors are unnecessary in these low power devices, resulting in structures equivalent to discrete transistors in complexity of fabrication. A low-current power supply is required for isolation purposes. Transistor characteristics differ negligibly from those of standard transistors at collector currents <0.05 mA, and are satisfactory for application in linear circuits at currents up to at least 0.1 mA. Transistor fTis 80 MHz at 0.1 mA emitter current, 2 V collector voltage.     

A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

Design of noise detector circuits as compact as standard logic cells is proposed. High-density large-scale digital integrated circuits that embed such built-in noise detectors enable in-depth characterization of dynamic power supply and ground noises. Dependence of power supply and ground voltage drops on the location of active cell rows within 1.8-V standard cell-based digital circuits are consistently measured by 1.8- and 2.5-V built-in detectors fabricated in a 0.18-/spl mu/m CMOS triple-well technology. Measurements also show that ground noise distribution is distinctively more localized than power supply counterparts due to the presence of a substrate.     

Selective ion implantation to reduce power consumption in MOS integrated circuits

A method of using implantation to reducek'in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.     

Frequency properties of on-die power distribution network in VLSI circuits

The local voltage fluctuations in the supply and ground grids triggered by on-die logic cell switching in VLSI devices have been experimentally studied. The results show that these fluctuations have a resonant-like form i.e., the on-die power grid should be described as an RLC circuit. The studies reveal that the active element (i.e., CMOS logic cell) affects the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). It is demonstrated that the frequency properties of the both grids are inter-related via the interconnecting active elements.     

RESURF LDMOSFET with a trench for SOI power integrated circuits

A new structure of RESURF LDMOSFET is proposed, based on silicon-on-insulator, to improve the characteristics of the breakdown voltage and the specific on-resistance, where a trench is applied under the gate in the drift region. A trench is used to reduce the electric field under the gate when the concentration of the drift region is high, thereby increasing the breakdown voltage and reducing the specific on-resistance. Detailed numerical simulations demonstrate the characteristics of this device and indicate an enhancement on the performance of the breakdown voltage and the specific on-resistance in comparison with an optimal conventional device with LOCOS under the gate.     

Pulsed ionizing radiation recovery characteristics of MSI GaAs integrated circuits

GaAs Schottky Diode FET Logic Divide-by 8 circuits have been characterized for transient response when exposed to 20 ns FXR pulses at 25°C. A logic upset threshold of about 10⁸rad/s was observed. At dose rates of 2 × 10¹⁰rads/s, functional operation was restored in 5 µs. A discussion of logic upset mechanisms is presented, attempting to explain both short and long term recovery observations.     

Designing power supply clamps for electrostatic discharge protection of integrated circuits

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.     

An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits

Digital power supply noise is a key issue in the design of mixed-signal and radio frequency (RF) integrated circuits (IC). In this paper, we have evaluated the impact of different digital design alternatives and technological parameters on the noise power spectral density. Related rules guiding designers to minimise the effect of digital noise on the analogue RF section conclude the work.     

Experimental model aid for planar design of transistor characteristics in integrated circuits

A two-transistor lumped model is used to describe the main features of transistors' two dimensional action. The model provides a first order correction to the ideal one dimensional transistor gain due to the effect of the emitter periphery. The correction is given in terms of a single parameter which can be experimentally evaluated for a fixed diffusion process. This makes the model a practical tool in I.C. transistor layout design. Experimental virification of the model is presented. Finally, implication to gain and cutoff frequency falloff due to lateral injection at high current is suggested.     

基于智能电网的综合通信系统简述

综合通信系统是智能电网中的重要组成部分,是建设智能电网以及实现其他应用技术的基础,是智能电网的核心技术之一。基于此,对智能电网中的综合通信系统进行简述。它是一个动态交互体系,实时反映电网信息和功率的变化,允许用户通过不同速度要求的互联应用软件,在系统中与各种高级电子设备互相配合,实时完成电网数据的获取与传输、保护与控制,将电网建设成一个具有较强交互能力和"即插即用"的综合性网络。由此可见:对综合通信系统的研究能够为建设智能电网做出必不可少的贡献。     

The explosion of resin moulded power integrated circuits and the corresponding countermeasures

Product Liability (PL) is one of the most serious problems at the present time, but the interest in it is mainly concerned with systems. The authors point out in this paper that one of PL problems is in the parts, namely, the explosion of resin moulded power integrated circuits. There are a few chances of explosion during the test of the units or sets into which they are assembled, due to misoperations such as shorting between the adjacent pins. At that time, a bonding wire or IC chip is overheated due to abnormally high current or power, then the resin fragment just above it is blown off into the air, sometimes burning. This situation is very dangerous and considered to have a possibility of someone becoming blinded.We clarified the explosion mechanism and present some counter-measures to prevent the explosion accident, i.e. some methods of explosion free devices and techniques preventing such accidents.     

Feedback supported isolation structure for blocking of minority leakage carriers in power integrated circuits

A combination of two conventional junction isolation structures is used to produce a device, which significantly improves the blocking of minority carriers injected into the substrate of a power IC due to switching of an inductive load. Simulation results show that the connection scheme employed greatly enhances the efficiency of the structures. A substrate current reduction of up to four orders of magnitude compared to conventional junction isolation structures is achieved. The significance of doping profiles in the p-sinker region is evaluated.     

Low power integrated circuits for an implantable pulsed Doppler ultrasonic blood flowmeter

Describes two custom integrated circuits which were developed for an implantable pulsed Doppler ultrasonic blood flowmeter. Prime design goals were a minimum circuit volume, minimum power consumption, and operation at low supply voltages. The first of the two IC's performs system timing functions and produces the ultrasonic transmit burst. It can deliver up to 40 mW of peak output power at 50 percent efficiency and requires 3.7 mW standby power. The second IC, containing an RF amplifier, mixer and output amplifier, provides 54 dB conversion voltage gain for an 0.8 MHz bandwidth centered at 5.8 MHz, <3 dB noise figure, a dynamic range of 40 dB, and 1 /spl mu/s recovery time from a 1 V overload. This chip requires 2.7 mW power input.