Wafer yield prediction using derived spatial variables

Unreliable chips tend to form spatial clusters on semiconductor wafers. The spatial patterns of these defects are largely reflected in functional testing results. However, the spatial cluster information of unreliable chips has not been fully used to predict the performance in field use in the literature. This paper proposes a novel wafer yield prediction model that incorporates the spatial clustering information in functional testing. Fused LASSO is first adopted to derive variables based on the spatial distribution of defect clusters. Then, a logistic regression model is used to predict the final yield (ratio of chips that remain functional until expected lifetime) with derived spatial covariates and functional testing values. The proposed model is evaluated both on real production wafers and in an extensive simulation study. The results show that by explicitly considering the characteristics of defect clusters, our proposed model provides improved performance compared to existing methods. Moreover, the cross‐validation experiments prove that our approach is capable of using historical data to predict yield on newly produced wafers.     

Recognition of defect spatial patterns in semiconductor fabrication

This research develops an analytical structure comprised of a filtering scheme and a fuzzy rule-based inference system to help identify defect spatial patterns. These defect spatial patterns include ring, scratch, zone and repeating types. A set of image processing masks is designed to locate defect positions and then the filtering scheme is applied to extract defect clusters on wafers. With clearly identified defect clusters, three features of minimum rectangle area are used to locate and describe the shape of defect clusters. When all possible defect clusters are well represented by minimum rectangle areas, a set of fuzzy rules are established to combine all the defect clusters and therefore defect spatial patterns are identified. The experiments show that the present approach can effectively identify different defect spatial patterns on wafers.     

Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers

The integrated circuits (ICs) on wafers are highly vulnerable to defects generated during the semiconductor manufacturing process. The spatial patterns of locally clustered defects are likely to contain information related to the defect generating mechanism. For the purpose of yield management, we propose a multi-step adaptive resonance theory (ART1) algorithm in order to accurately recognise the defect patterns scattered over a wafer. The proposed algorithm consists of a new similarity measure, based on the p-norm ratio and run-length encoding technique and pre-processing procedure: the variable resolution array and zooming strategy. The performance of the algorithm is evaluated based on the statistical models for four types of simulated defect patterns, each of which typically occurs during fabrication of ICs: random patterns by a spatial homogeneous Poisson process, ellipsoid patterns by a multivariate normal, curvilinear patterns by a principal curve, and ring patterns by a spherical shell. Computational testing results show that the proposed algorithm provides high accuracy and robustness in detecting IC defects, regardless of the types of defect patterns residing on the wafer.     

A generalised uncertain decision tree for defect classification of multiple wafer maps

Classification of defect chip patterns is one of the most important tasks in semiconductor manufacturing process. During the final stage of the process just before release, engineers must manually classify and summarise information of defect chips from a number of wafers that can aid in diagnosing the root causes of failures. Traditionally, several learning algorithms have been developed to classify defect patterns on wafer maps. However, most of them focused on a single wafer bin map based on certain features. The objective of this study is to propose a novel approach to classify defect patterns on multiple wafer maps based on uncertain features. To classify distinct defect patterns described by uncertain features on multiple wafer maps, we propose a generalised uncertain decision tree model considering correlations between uncertain features. In addition, we propose an approach to extract uncertain features of multiple wafer maps from the critical fail bit test (FBT) map, defect shape, and location based on a spatial autocorrelation method. Experiments were conducted using real-life DRAM wafers provided by the semiconductor industry. Results show that the proposed approach is much better than any existing methods reported in the literature.     

A novel hybrid resampling for semiconductor wafer defect bin classification

Generally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non-defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.     

A Spatial‐EWMA Framework for Detecting Clustering

Spatial surveillance is critical to health systems, manufacturing industries, and in many other domains. For example, determining hotspots of infectious diseases and detecting defect patterns on semiconductor wafers require sensitive spatial analysis tools. The goal of this paper is to detect spatial clusters with mean shifts. Conventional multivariate analysis methods may ignore spatial structure among data and lead to inefficient inspection. Several likelihood ratio‐based scan statistics have been designed for spatial surveillance. However, there is no most powerful test when parameters like shift magnitude and coverage are unknown. This paper proposes a spatial exponentially weighted moving average (spatial‐EWMA) approach that can detect the existence and locate the potential centers of shift clusters. The test procedure assigns different weights to the data with different radius levels from the investigated shift center. The efficiency of the spatial‐EWMA approach is shown by simulation. Lastly, an example of detecting the counties with high incidence of male thyroid cancer in New Mexico is provided to show the effectiveness of the proposed approach. Copyright © 2013 John Wiley & Sons, Ltd.     

Automatic identification of spatial defect patterns for semiconductor manufacturing

This research proposes an on-line diagnosis system based on denoising and clustering techniques to identify spatial defect patterns for semiconductor manufacturing. Today, even with highly automated and precisely monitored facilities used in a near dust-free clean room and operated with well-trained process engineers, the occurrence of spatial signatures on the wafer still cannot be avoided. Typical defect patterns shown on the wafer, including edge ring, linear scratch, zone type and mixed type, usually contain important information for quality engineers to remove their root causes of failures. In this paper, a spatial filter is simultaneously used to judge whether the input data contains any systematic cluster and to extract it from the noisy input. Then, an integrated clustering scheme combining fuzzy C means (FCM) with hierarchical linkage is adopted to separate various types of defect patterns. Furthermore, a decision tree based on two cluster features (convexity and eigenvalue ratio) is applied to a separated pattern to provide decision support for quality engineers. Experimental results show that both real dataset and synthetic dataset have been successfully extracted and classified. More importantly, the proposed method has potential to be further applied to other industries, such as liquid crystal display (LCD) and plasma display panel (PDP).     

A discrete spatial model for wafer yield prediction

Yield analysis is one of the key concerns in the fabrication of semiconductor wafers. An effective yield analysis model will contribute to production planning and control, cost reductions and the enhanced competitiveness of enterprises. In this article, we propose a novel discrete spatial model based on defect data on wafer maps for analyzing and predicting wafer yields at different chip locations. More specifically, based on a Bayesian framework, we propose a hierarchical generalized linear mixed model, which incorporates both global trends and spatially correlated effects to characterize wafer yields with clustered defects. Both real and simulated data are used to validate the performance of the proposed model. The experimental results show that the newly proposed model offers an improved fit to spatially correlated wafer map data.     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

A system for online detection and classification of wafer bin map defect patterns for manufacturing intelligence

Wafer bin maps (WBM) in circuit probe (CP) tests that present specific defect patterns provide crucial information to identifying assignable causes in the semiconductor manufacturing process. However, most semiconductor companies rely on engineers using eyeball analysis to judge defect patterns, which is time-consuming and not reliable. Furthermore, the conventional statistical process control used in CP tests only monitors the mean or standard deviation of yield rates and failure percentages without detecting defect patterns. To fill the gap, this study aims to develop a manufacturing intelligence solution that integrates spatial statistics and neural networks for the detection and classification of WBM patterns to construct a system for online monitoring and visualisation of WBM failure percentages and corresponding spatial patterns with an extended statistical process control chart. An empirical study was conducted in a leading semiconductor company in Taiwan to validate the effectiveness of the proposed system. The results show its practical viability and thus the proposed solution has been implemented in this company.     

Detection and classification of defect patterns on semiconductor wafers

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only expensive and time consuming but also it leads to high misidentification levels. In this paper, an automatic approach consisting of a spatial filter, a classification module and an estimation module is proposed to validate both real and simulated data. Experimental results show that three types of typical defect patterns: (i) a linear scratch; (ii) a circular ring; and (iii) an elliptical zone can be successfully extracted and classified. A Gaussian EM algorithm is used to estimate the elliptic and linear patterns, and a spherical-shell algorithm is used to estimate ring patterns. Furthermore, both convex and nonconvex defect patterns can be simultaneously recognized via a hybrid clustering method. The proposed method has the potential to be applied to other industries.     

Markov Random Fields in Pattern Recognition for Semiconductor Manufacturing

Under the most general conditions of an anisotropic Markov random field, we model the two-dimensional spatial distribution of microchips on a silicon wafer. The proposed model improves on its predecessors as it stipulates the spatial correlation of different strengths in all eight directions. Its canonical parameters represent the intensity of failures, main effects, and interactions of neighboring chips. Explicit forms of conditional distributions are derived, and maximum pseudo-likelihood estimates of canonical parameters are obtained. This numerical characteristic summarizes general patterns of clusters of failing chips on a wafer, capturing their size, shape, direction, density, and thickness. It is used to classify incoming wafers to known root-cause categories by matching them to the closest pattern.     

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently, machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductor manufacturing. The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features. This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns. First, the number of defects during the actual process may be limited. Therefore, insufficient data are generated using convolutional auto-encoder (CAE), and the expanded data are verified using the evaluation technique of structural similarity index measure (SSIM). After extracting handcrafted features, a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction. Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns, the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.     

Monocrystalline silicon used for integrated circuits: still on the way

With the rapid development of semiconductor technology, highly integrated circuits (ICs) and future nano-scale devices require large diameter and defect-free monocrystalline silicon wafers. The ongoing innovation from silicon materials is one of the driving forces in future micro and nano-technologies. In this work, the recent developments in the controlling of large diameter silicon crystal growth processes, the improvement of material features by co-doping with the intend-introduced impurities, and the progress of defect engineered silicon wafers (epitaxial silicon wafer, strained silicon, silicon on insulator) are reviewed. It is proposed that the silicon manufacturing infrastructure could still meet the increasingly stringent requirements arising from ULSI circuits and will expand Moore’s law into a couple of decades.     

Monocrystalline silicon used for integrated circuits: still on the way

With the rapid development of semiconductor technology, highly integrated circuits (ICs) and future nano-scale devices require large diameter and defect-free monocrystalline silicon wafers. The ongoing innovation from silicon materials is one of the driving forces in future micro and nano-technologies. In this work, the recent developments in the controlling of large diameter silicon crystal growth processes, the improvement of material features by co-doping with the intend-introduced impurities, and the progress of defect engineered silicon wafers (epitaxial silicon wafer, strained silicon, silicon on insulator) are reviewed. It is proposed that the silicon manufacturing infrastructure could still meet the increasingly stringent requirements arising from ULSI circuits and will expand Moore’s law into a couple of decades.     

Stability-integrated Fuzzy <Emphasis Type="Italic">C</Emphasis> means segmentation for spatial incorporated automation of number of clusters

Fuzzy C Means clustering, one of the predominant segmentation algorithms, requires prior knowledge of number of clusters in the image and is sensitive to noise and outliers. Determining the number of clusters and including spatial information to basic Fuzzy C Means clustering are done in numerous ways. Literature reveals that either number of clusters is defined or spatial information is incorporated. In the proposed work, spatial information and cluster determination are integrated based on the concept of stability. Implementation of split and merge algorithm to find the number of clusters is done based on the modified Sylvester’s theorem in the context of positive definite functions. Experiments are performed on synthetic and real images and the number of clusters determined is validated using validation indices. Results show that correct clusters are classified with robustness to noise.     

Scheduling and optimization of mixed-processing with multi-variety wafers in dual-armed cluster tools

ABSTRACT

To improve the efficiency of wafer fabrication, this work addresses the scheduling and control problems of mixed-processing with multiple wafer types in cluster tools. Then, based on a developed Petri net (PN) model, it presents a general model for cluster tools with multiple wafer types and the conventional swap strategy. By analyzing the coordination mechanism between wafers processing and robot tasks, necessary and sufficient conditions are established to check the schedulability of the system that is operated by using the conventional swap strategy. If the system is not schedulable checked by such schedulability conditions, a constraint-guided heuristic algorithm and a conflicts-avoiding algorithm are developed to obtain a reasonable schedule. Finally, illustrative examples are presented to show the applications of the proposed method.     

Dynamic model of three-dimensional cluster formation

A discrete three-dimensional model has been developed for the computer simulation of multistage processes involved in the formation of a porous space in semiconductor crystals anodized in a reactive medium. A related program package is created that provides the dynamic simulation of cluster formation in depth of a semiconductor crystal with allowance for the processes taking place on the surface, chemical reactions accompanying these processes, and applied external fields. The maximum fractal dimension of structures obtained using this algorithm within the framework of the proposed model is 2.68.     

Modelling and scheduling analysis of multi-cluster tools with residency constraints based on time constraint sets

This paper is dedicated to the scheduling problem of multi-cluster tools with process module residency constraints and multiple wafer product types. The problem is formulated as a non-linear programming model based on a set of time constraint sets. An effective algorithm called the time constraint sets based (TCSB) algorithm is presented as a new method to schedule the transport modules to minimise the makespan of a number of wafers. In approach, time constraint sets are maintained for all the resources and necessary operations to exploit the remaining production capacities during the scheduling process. To validate the proposed algorithm on a broader basis, a series of simulation experiments are designed to compare our TCSB algorithm with the benchmark with regard to cluster factor, configuration flexibilities and the variation of the processing times and residency constraint times. The results indicate that the proposed TCSB algorithm gives optimal or near optimal scheduling solutions in most cases.     

An improved imperialist competitive algorithm based photolithography machines scheduling

Abstract: Photolithography machine is one of the most expensive equipment in semiconductor manufacturing system, and as such is often the bottleneck for processing wafers. This paper focuses on photolithography machines scheduling with the objective of total completion time minimisation. In contrast to classic parallel machines scheduling, it is characterised by dynamical arrival wafers, re-entrant process flows, dedicated machine constraints and auxiliary resources constraints. We propose an improved imperialist competitive algorithm (ICA) within the framework of a rolling horizon strategy for the problem. We develop a variable time interval-based rolling horizon strategy to decide the scheduling point. We address the global optimisation in every local scheduling by proposing a mixed cost function. Moreover, an adaptive assimilation operator and a sociopolitical competition operator are used to prevent premature convergence of ICA to local optima. A chaotic sequence-based local search method is presented to accelerate the rate of convergence. Computational experiments are carried out comparing the proposed algorithm with ILOG CPLEX, dispatching rules and meta-heuristic algorithms in the literature. It is observed that the algorithm proposed shows an excellent behaviour on cycle time minimisation while with a good on time delivery rate and machine utilisation rate.