FPGA在实时图像预处理中的应用

实时图像处理通常需要巨大的数据吞吐量和运算量。因此专用的硬件或者多重处理技术的并行处理很必要。描述了一个基于现场可编程门阵列(FPGA)的灵活的可编程图像处理系统。FPGA特有的逻辑结构单元对实现实时图像处理来说有着先天的优势。在此,我们提出一个通用的实时图像处理模型,并在FPGA上实现了中值滤波算法,从而对采集的实时图像作预处理。     

Parallel Image Processing Technology of Surface Detection System

To improve image processing speed and detection precision of a surface detection system on a strip surface, based on the analysis of the characteristics of image data and image processing in detection system on the strip surface, the design of parallel image processing system and the methods of algorithm implementation have been studied. By using field programmable gate array（FPGA） as hardware platform of implementation and considering the characteristic of detection system on the strip surface, a parallel image processing system implemented by using multi IP kernel is designed. According to different computing tasks and the load balancing capability of parallel processing system, the system could set different calculating numbers of nodes to meet the system＇s demand and save the hardware cost.     

基于FPGA的多功能图像处理系统设计

采用FPGA取代计算机实现高分辨率图像的采集、处理和显示可以解决图像采集速度慢和图像品质低的问题。实现了视频信号的采集、存储、反馈控制传感器、图像增强以及液晶显示.详细介绍了系统硬件组成结构,并分析其硬件原理.FPGA具有易擦写和逻辑规模大的特点.处理结果可以通过串口、USB口和上位机通讯并且可以实现板上大容量存储.系统具有集成度高、应用度广、使用灵活等特点.     

基于FPGA的实时幸运区域融合算法

大气湍流对光学目标图像的分辨率会产生随机性 的影响。幸运区域融合(lucky-region fusion,LRF)是一 种针对受大气湍流影响图像序列的图像合成技术,通过在一系列短曝光图像中选取具有高分 辨率的区域进行融合,从而获得一张清晰的图像。LRF 算法在台式计算机上实现比较简单, 但这是事后处理的方法,没有实时性。描述一种针对灰度图像流实时地进行提取、分区处理 和合成的LRF算法及其系统实现技术。根据现场可编程门阵列(field programmable gate array,FPGA)数字信号处理的特点 , 提出了一种适合于FPGA处理的实时LRF算法。用硬件描述语言对该算法进行逻辑设计,将 其嵌入到一个中小规模的FPGA上,从而构成一个纯硬件的紧凑的LRF处理系统。通过模拟 的序列图像和在实验室实际拍摄了短曝光序列图像,对该系统进行了测试。实验结果表明, 所提出的实时LRF算法可行,所实现的FPGA系统可以实现输入灰度图像序列的实时动态幸 运区域融合,并最终获得高分辨率的融合图像。     

FPGA在机载雷达信号处理系统中的应用

介绍了一种基于大规模FPGA及高性能DSP芯片的机载雷达信号处理嵌入式系统的设计方案及设计实现。采用标准的VME总线及基于FPGA内嵌MGT的高速串行互连技术，具有实时性强、集成度高以及软硬件可编程易于系统扩展及重构的特点。     

LTE基站中PDSCH高效并行计算的FPGA实现

提出一种第三代合作伙伴(3GPP)长期演进(LTE)基站中下行共享信道(PDSCH)中比特级信号处理并行计算方案,其并行运算是基于现场可编程门阵列(FPGA)的。由于下行控制信道中数据流量相对下行共享信道偏少,为了保证控制信道与共享信道下行数据的时序对齐,并且最大程度上节省硬件资源,以满足LTE系统测试要求,必须采用并行计算的处理方式。采用VHDL语言在Xilinx公司的Virtex-6系列FPGA芯片内成功对该方案进行了验证,并对其进行优化。     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.     

基于多DSP与FPGA的实时图像处理系统设计

为解决高速数字图像处理系统和实时性相冲突的要求,设计了以多DSP（数字信号处理器TMS320C6416）和现场可编程门阵列（FPGA）相结合的实时图像处理系统。重点介绍了该系统的硬件资源选择、基本组成、工作原理、电源设计、DSP引导方式以及软件设计等,通过对每秒25帧14位640×512像素的数字图像处理结果表明,该系...     

高速多通道CCD图像数据处理与传输系统设计

针对航天光学遥感成像系统输出通道多、输出速率高的特点,提出一种高速、多通道CCD图像数据并行处理与传输系统的设计方案.该方案以FPGA为数据处理和控制核心,采用基于FPGA区域并行处理的数据处理方法,运用FPGA内部块RAM构建高速多通道CCD图像的缓冲区,在存取控制上采取区域缓存和时分复用的策略完成对高速多通道CCD...     

Design and implementation of a high level programming environmentfor FPGA-based image processing

Reconfigurable hardware in the form of field programmable gate arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution. However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, the authors present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Their approach is to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations     

A novel FPGA-based architecture for Sobel edge detection operator

A novel FPGA-based architecture for Sobel edge detection algorithm has been proposed. The Sobel algorithm is chosen due to its property of providing a differencing as well as noise smoothing operation in the single kernel. Thus, noise sensitivity of first gradient based operations can be avoided by the use of this algorithm. The implementation of edge detection algorithms on a field programmable gate array (FPGA) is motivated by the fact that large memory FPGAs are now available, providing a platform for processing real time algorithms on application-specific hardware with substantially higher performance than programmable digital signal processors (DSPs). This architecture can be used as a building block of a pattern recognition system, autonomous robot navigation, and also as a system for creating an image dazzling effect in multimedia graphics. This architecture is implicitly pipelined to provide a system capable of operating at a clock speed of 99.499?MHz which is a significant improvement over programmable DSPs implementation.     

基于NIOSⅡ的红外弱小目标检测算法实现

介绍了基于可编程片上系统SOPC技术的图像处理系统的软硬件设计,系统采用FPGA作为视频信号采集控制模块,利用FPGA内建NIOSⅡ软核微控制器作为图像处理单元。针对天空背景下红外弱小目标,提出了一种基于形态学和仿生学相结合的图像预处理算法,该算法在基于数学形态学滤波的基础上利用人眼固视微动辨别信息的原理对图像进行背景抑制和目标增强;采用自适应阈值分割法确定目标。硬件实验结果表明系统实时性好,图像处理效果良好,目标检测率高,验证了预处理算法的有效性和实时性。     

图像采集系统中色彩复原模块的FPGA实现

图像的色彩复原是彩色图像采集系统的关键技术,决定了采集图像的质量.针对目前CMOS图像传感器广泛使用的Bayer格式图像,介绍了双线性插值法、梯度检测插值法和相关性插值法三种色彩复原算法:然后建立了基于Altera公司Cydone Ⅱ系列FPGA芯片的图像采集系统.并采用Verilog硬件描述语言在FPGA上实现了色彩复原算法.实验结果表明,该FPGA利用其丰富的内部硬件资源和并行处理的优势,能实时准确地完成色彩复原工作,同时,相关性插值法获得了最高峰值信噪比.恢复的彩色图像边缘清晰平滑.     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

FPGA-based Personal Authentication Using Fingerprints

The current technological age demands the deployment of biometric security systems not only in those stringent and highly reliable fields (forensic, government, banking, etc.) but also in a wide range of daily use consumer applications (internet access, border control, health monitoring, mobile phones, laptops, etc.) accessible worldwide to any user. In order to succeed in the exploitation of biometric applications over the world, it is needed to make research on power-efficient and cost-effective computational platforms able to deal with those demanding image and signal operations carried out in the biometric processing. The present work deals with the evaluation of alternative system architectures to those existing PC (personal computers), HPC (high-performance computing) or GPU-based (graphics processing unit) platforms in one specific scenario: the physical implementation of an AFAS (automatic fingerprint-based authentication system) application. The development of automated fingerprint-based personal recognition systems in the way of compute-intensive and real-time embedded systems under SoPC (system-on-programmable-chip) devices featuring one general-purpose MPU (microprocessor unit) and one run-time reconfigurable FPGA (field programmable gate array) proves to be an efficient and cost-effective solution. The provided flexibility, not only in terms of software but also in terms of hardware thanks to the programmability and run-time reconfigurability performance exhibited by the suggested FPGA device, permits to build any application by means of hardware-software co-design techniques. The parallelism and acceleration performances inherent to the hardware design and the ability of reusing hardware resources along the application execution time are key factors to improve the performance of existing systems.     

基于FPGA和DSP的高速图像处理系统

为了提高图像处理系统的高性能和低功耗,提出了一种基于FPGA和DSP协同作业的高速图像处理嵌入式系统,其中DSP为主处理器,负责图像处理,而FPGA为协处理器,负责系统的所有数字逻辑。整个系统中FPGA和DSP的工作之间形成流水,同时借助于单片双口RAM(CY7C025AV-15AI)完成两者的通信,比使用单片DSP建立的处理系统性能提高25%左右。该系统具有可重构性,方便其他的算法于该系统上实现。     

A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O

A system chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and an SRAM-based embedded field-programmable gate array (FPGA). Application-specific bus-mapped coprocessors and flexible input/output peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customization. The silicon area required by the system is 20 mm/sup 2/ in a 0.18-/spl mu/m CMOS technology. The embedded FPGA accounts for about 40% of the system area.     

基于FPGA的二值图像连通域快速标记

针对连通域标记算法运算量大、速度慢、硬件实现困难的缺点,提出一种适于现场可编程逻辑门阵列（FPGA）实现的二值图像连通域快速标记的算法,并用VHDL硬件开发语言在XILINX公司的FPGA上实现。实验结果表明了该算法能对二值图像复杂的连通关系正确标记,易于硬件实现,大大节约了硬件资源,电路结构简单,满足实时性要求。     

基于TMS320C6203 DSP的实时红外图像处理系统

遵从模块化设计思想,提出了以11公司的高性能数字信号处理器TMS320C6203为核心器件的实时红外图像处理系统的设计方案,结合大规模可编程逻辑阵列CPLD进行逻辑控制和现场可编程门阵列FPGA对采集的红外图像进行预处理,完成对图像的实时采集和图像目标的实时处理。