一种双超级电容倍压式串联蓄电池系统并行均衡器

传统电容式串行均衡器利用串联单体蓄电池间的电压差实现单体蓄电池间的串行均衡,由于串联单体蓄电池之间电压差小,该均衡器能量均衡效率低、均衡速度慢.为此,提出一种双超级电容倍压式串联蓄电池系统并行均衡器,该均衡器具有以下2种工作模式:多个单体蓄电池并行均衡放电的双超级电容并联储能、多个单体蓄电池并行均衡充电的双超级电容串联释能.所提出的并行均衡策略能够极大地提高均衡速度,同时双电容使电容均衡的储能能力加倍,且均衡性能不受单体蓄电池间电压差小的限制.详细介绍了均衡器结构、工作原理和控制策略.搭建了4个串联锂离子蓄电池均衡器实验平台并设计了样机进行实验,结果证明了所提均衡器的可行性与优越性.     

Design of a ZVS PWM DC–DC converter for high gain applications

In this paper, a pulse width modulation DC‐DC converter with high step‐up voltage gain is proposed. The proposed converter achieves high step‐up voltage gain with appropriate duty ratio, coupled inductor, and voltage multiplier technique. The energy stored in the leakage inductor of the coupled inductor can be recycled in the proposed converter. Moreover, because both main and auxiliary switches can be turned on with zero‐voltage switching, switching loss can be reduced by soft‐switching technique. So the overall conversion efficiency is improved significantly. The theoretical steady‐state analyses and the operating principles of the proposed converter are discussed in detail for both continuous conduction mode and discontinuous conduction mode. Finally, a laboratory prototype circuit of the proposed converter is implemented to verify the performance of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of high‐speed low‐power parallel‐prefix adder trees in nanometer technologies

This paper presents a novel approach to design high‐speed low‐power parallel‐prefix adder trees. Sub‐circuits typically used in the design of parallel‐prefix trees are deeply analyzed and separately optimized. The modules used for computing the group propagate and generate signals have been designed to improve their energy‐delay behavior in an original way. When the ST 45 nm 1 V CMOS technology is used, in comparison with conventional implementations, the proposed approach exhibits computational delay with mean value and standard deviation up to 40% and 48% lower and achieves energy consumption with mean value and standard deviation up to 57% and 40% lower. A 32‐bit Brent‐Kung tree made as proposed here reaches a computational delay lower than 165 ps and dissipates 147.4fJ on average. Copyright © 2013 John Wiley & Sons, Ltd.     

Electric double‐layer capacitor module with series‐parallel reconfigurable cell voltage equalizers

When electric double‐layer capacitors (EDLCs) are connected in series, a cell voltage imbalance occurs due to nonuniform cell properties. Cell voltage imbalance should be minimized to prolong cycle lives and maximize the available energy of cells. In this study, we propose a series‐parallel reconfigurable cell voltage equalizer that is considered suitable for energy storage systems using EDLCs instead of traditional secondary batteries as the main energy storage sources. The proposed equalizer requires only EDLCs and switches as its main circuit elements, and it utilizes EDLCs not only for energy storage but also for equalization. An equivalent circuit model using equivalent resistors that can be regarded as an index of equalization speed is developed. Current distribution and cell voltage imbalancing during operation are quantitatively generalized. Experimental charge–discharge tests were performed on the EDLC modules to demonstrate the performance of the cell voltage equalizer. All the cells in the modules could be charged/discharged uniformly even when a degradation‐mimicking cell was intentionally included in the module. The resultant cell voltage imbalances and current distributions were in good agreement with those predicted by mathematical analyses. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(4): 38–50, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21287     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel analog switch for high‐precision switched‐capacitor applications

The performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of ?81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.     

The parallel operation control of a modular AC to DC converter via serial communication bus

This paper presents the parallel operation control of a modular AC to DC converter via a serial communication bus. In the proposed system, multiple AC to DC converters are parallel‐connected at the output end for load current sharing. Each module of the AC to DC converter is controlled by its individual microcontroller. The microcontroller of each module is employed for the voltage control loop and communicates with the microcontrollers of the other converter modules. The RS485 serial communication is used to transmit information among the controllers, which checks the number of the converter module for calculating the input inductor current command of each converter module. Moreover, the clock signal is used for synchronization to prevent data collision on the serial communication bus. The proposed parallel operation control provides fast response when the converter module connects or disconnects according to the required power. The performance evaluation of the proposed system is conducted by simulation and experimental verification on two parallel isolated CUK converters. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A novel charging/discharging balancing strategy for lithium battery pack based on mixed charging mode

Series‐connected lithium batteries can be charged in the pack‐charging mode, which is most widely used in the lithium battery application field. But the pack‐charging mode will lead to cell imbalance because of the difference in the electrochemical characteristics of the cells of series‐connected batteries. On the other hand, the cell‐charging mode can avoid the imbalance problem by charging each cell independently, but it will reduce the charging efficiency and increase the cost. In this paper, a novel balancing strategy is proposed with a mixed pack‐charging and cell‐charging mode to implement the balancing algorithm. The proposed strategy aims to solve the problem of charge/discharge imbalance with the simplest balancing algorithm with high balancing performance. There is no complex balancing behaviors during the charging process – as is the case with many other existing schemes – so the control algorithm can be greatly simplified. Because each cell can be fully charged and discharged with the proposed algorithm, it helps to make full use of the energy and capacity of each cell. The system stability and reliability of the proposed system, as well as its good performance, are verified through experiments. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Optimal current control methods of a non‐salient pole hybrid field‐synchronous motor for energy‐efficient and wide speed‐range operation

This paper proposes new practical optimal current control methods for a newly emerging class of non‐salient pole synchronous motors with hybrid rotor fields by both permanent magnet and winding. In practical situations with limited voltage, the extensively used permanent magnet synchronous motor hardly achieves an ideal performance that allows simultaneously both low‐speed high‐torque and wide speed‐range operations, due to its constant magnet field. Hybrid field synchronous motors (HFSM) have recently emerged to achieve ideal performance as practical motors with controllable hybrid rotor field. For HFSM, the same torque can be produced by a variety of currents due to nonlinearity between torque and currents. Consequently, appropriate determination of a set of stator and rotor current commands plays a key role in achieving possible energy‐efficient and wide speed‐range operation. Proposed methods determine the current commands corresponding to a given torque command such that total winding copper loss due to stator and rotor currents can be minimized if the exact solution exists; the best approximate torque can be produced if no exact solution exists. The determined current commands are optimal in the sense of energy efficiency or degree of approximation in wide speed‐range operation under voltage limit. New real‐time recursive algorithms searching the optimal current solution are also given. The proposed methods are analytical but practical, and their usefulness is verified through experiments. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 156(1): 70–83, 2006; Published online in Wiley InterScience ( www.interscience. wiley.com ). DOI 10.1002/eej.20156     

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits

In this paper, we proposed a high‐performance, high‐precision power supply noise (PSN) detector by using dual peak detection sample and hold circuits with source follower. By using dual peak detection sample and hold circuits, we can avoid PSN missing detection and therefore avoid massive PSN detection error. We also added one dummy switch to cancel the charge injection effect and to improve the PSN detection accuracy. In the proposed design, we applied one PMOS type charging circuit to enhance the operation frequency of differential amplifier, which can widen both the PSN detection bandwidth and the detection range. As a result, in the proposed PSN detection circuit, the PSN detection bandwidth can be raised from 1 GHz to 2 GHz with the PSN detection error lowered to ±3%. Moreover, the PSN detection range is widened from 10%–50%VDD to 5%–65%VDD as compared with the state‐of‐the‐art design. Copyright © 2012 John Wiley & Sons, Ltd.     

A framework for high‐speed parallel‐prefix adder performance evaluation and comparison

A new framework is proposed for the evaluation and comparison of high‐speed parallel‐prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy‐efficient 64‐bit carry select adder with distributed mixed valence logic to help reduce fan‐out and wire load is presented. Footless pulsed‐precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65 nm CMOS models are compared with other parallel‐prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge‐Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright © 2014 John Wiley & Sons, Ltd.     

Parallelization of the Nanoelectronic Modeling Tool (NEMO 1-D) on a Beowulf Cluster

NEMO's main task is the computation of current-voltage (I-V) characteristics for resonant tunneling diodes (RTDs). The primary model for high performance RTDs is the full band sp3s* tight binding simulation, which is based on a numerical double integral of energy and transverse momentum over a transport kernel at each bias point. A full charge self-consistent simulation invoking this model on a single CPU is prohibitively expensive, as the generation of a single I-V curve would take about 1–2 weeks to compute. Simplified charge self-consistent models, eliminating the numerical momentum integral for the quantum mechanical charge self-consistency, followed by a single pass double integration for the current, have been used in the past. However, Computation on a parallel computer now enables the thorough exploration of quantum mechanical transport including charge self-consistency effects within the entire Brillouin zone based on the double integral. Various parallelization schemes (fine, coarse, and mixed) are presented and evaluated in their performance. Finally a comparison to experimental data is given.     

Structure and Characteristics of High‐Performance PMASynRM with Ferrite Magnets

Recently, the use of permanent magnet (PM) motors has risen markedly because of improvements in the performance of rare earth PM motors. However, the use of rare earth materials, which is an important aspect of the high‐performance PM motor, should be reduced because of the high cost and unpredictability associated with procuring such materials. The performance of motors that use rare earth materials has reached a very high level, one that will not be easy to match without such materials. In this paper, we propose a structure for a high‐power‐density PM‐assisted synchronous reluctance motor involving the use of a ferrite PM. The structure prevents irreversible demagnetization of the PM even in the presence of heavy flux‐weakening excitation or an inverter fault. It is shown that the proposed structure achieves high‐power and high‐efficiency performance. © 2014 Wiley Periodicals, Inc. Electr Eng Jpn, 187(1): 42–50, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22362     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.     

A bidirectional DC/DC converter charge/discharge controller for solar energy illumination system integrating synchronous rectification SEPIC converter and active clamp flyback converter

This paper presents a novel bidirectional DC‐to‐DC converter charge/discharge controller for solar energy illumination system. The bidirectional converter architecture integrates the synchronous rectification Single Ended Primary Inductor Converter (SEPIC) converter and an active clamp flyback converter. In addition to fully use the properties of the shared components and compensate for the shortcomings of conventional two‐stage illumination systems, the proposed system has the advantages of soft‐switching, simple structure, and high efficiency. During daytime, a SEPIC converter with synchronous rectification function was used to charge the lead acid battery through three‐stage charging and maximum power point tracking. At night, the battery discharges, driving and dimming high‐brightness LEDs using the active clamp flyback converter. Finally, a solar energy illumination system with both a 160 W charge/discharge controller and an 80 W LED driver was implemented to verify the feasibility and practicality of the proposed system. Copyright © 2015 John Wiley & Sons, Ltd.     

A new separate‐identification method of two stator equivalent core‐loss resistances corresponding to hysteresis and eddy‐current losses for parallel‐type mathematical models of AC motors

This paper proposes a new unified method for identifying equivalent stator core‐loss resistance of AC motors, which can be applied to both induction and synchronous motors. In order to realize AC motors that exhibit high performance such as precise torque generation and/or efficient energy transmission, stator core loss cannot be neglected in designing vector control systems. It is common to model stator core loss in magnetic circuits as loss caused by equivalent resistance in electrical circuit. One of the best mathematical models for controlling AC motors with core loss is a kind of parallel‐type model that succeeds in modeling both eddy‐current and hysteresis losses. The newly proposed method succeeds in identifying separately and simultaneously two kinds of equivalent core‐loss resistances on the model corresponding to eddy‐current and hysteresis losses. The practical usefulness of the method is evaluated and confirmed through experiments using two induction motors of 5.5 and 2.0 kW having relatively high core losses and a permanent magnet synchronous motor of 750 W having relatively low core losses. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 143(4): 50–63, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10152     

微电网混合储能系统控制策略研究

微电网中的微电源和负载具有波动性和随机性,故储能系统是维持微电网安全可靠运行并改善电能质量的关键,蓄电池与超级电容器混合使用可以发挥蓄电池电池能量密度大和超级电容器功率密度大,充放电速度快的优势,提高微电网储能系统性能。提出了一种基于互补PWM小信号模型,并分别给蓄电池和超级电容器设计了控制方案,蓄电池采用单电流环很好的平抑了功率的低频波动,超级电容器采用带前馈的双环控制,平抑功率的高频波动,并有效的维持了直流母线电压的稳定。仿真结果证明了所提出的控制策略的正确性。     

Analysis and design of discrete‐time charge domain filters with complex conjugate poles

This paper proposes a discrete‐time charge domain filter that achieves complex conjugate poles in the transfer function of the filter. To achieve complex conjugate poles, local feedbacks are inserted around two successive discrete‐time integrators. The feedback path is implemented through a transconductance cell which applies a continuous time current into the integrators. Analytical models have been proposed to approximate the behavior of the filter. These models confirm that the structure is capable of realizing complex poles and thus can be used to synthesize any type of filter structures such as Butterworth, Chebysheve, etc. To show the effectiveness of the proposed architecture, Butterworth filters of order 2 and 4 operating at 50MS/s are designed and implemented in 180‐nm CMOS technology with 1.8‐V power supply. The effect of circuit nonidealities on the performance of the filter is analyzed and verified through simulations. Simulation results show that a conventional charge domain filter can be simply extended to implement complex conjugate poles while the noise and linearity performance of the filter are also improved. Copyright © 2016 John Wiley & Sons, Ltd.     

A fully differential current copier for performance improvement

This paper presents a new current copier which uses a differential‐pair as its storage cell. The differential‐pair storage unit (DPSU) significantly reduces clock‐feedthrough errors and achieves high linearity, large dynamic range, and less cross‐talk noise. Therefore, the proposed high‐performance DPSU can be used to improve the speed performance of analog‐to‐digital converters which implement the proposed fully differential switched‐current technique. Copyright © 2000 John Wiley & Sons, Ltd.