A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

A novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit with n_c pumping capacitors and (ii) a switched‐inductor booster with m_c resonant capacitors, so as to obtain the high step‐up gain of (n_c + 1) × m_c /(1 ? D) at most, where D is the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage number n (n = 0, 1, 2, …, n_c) of pumping capacitors to obtain a flexible gain of (n + 1) × m_c /(1 ? D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.     

A gain/efficiency‐enhanced bidirectional switched‐capacitor DC‐DC converter

A closed‐loop gain/efficiency‐enhanced bidirectional switched‐capacitor converter (BSCC) is proposed by combining an adaptive‐conversion‐ratio (ACR) phase generator and pulse‐width‐modulation (PWM) controller for bidirectional step‐up/down DC‐DC conversion and regulation. For realizing gain‐enhanced, the power part consists of one m_c‐stage cell and one n_c‐stage cell in cascade between low‐voltage (LV) and high‐voltage (HV) sides to boost HV voltage into m_c × n_c times voltage of LV source at most, or convert LV voltage into 1/(m_c × n_c) times voltage of HV source at most. For realizing efficiency‐enhanced, the ACR idea with adapting stage number m, n is built in the phase generator to obtain a suitable step‐up/down gain: m × n or 1/(m × n) (m = 1, 2, …, m_c, n = 1, 2, …, n_c). Further, the output regulation and robustness to source/loading variation can be enhanced by PWM on the LV/HV sides. Some theoretical analysis and control design are included as: modeling, steady‐state analysis, conversion ratio, efficiency, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a BSCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Multistage multiphase switched‐capacitor DC–DC converter with variable‐phase and PWM control

A closed‐loop multistage multiphase switched‐capacitor converter (n‐stage p‐phase MPSC) is proposed with a variable‐phase control (VPC) and a pulse‐width‐modulation (PWM) technique for low‐power step‐up conversion and high‐efficiency regulation. In this n‐stage MPSC, n voltage doublers are connected in series for boosting the voltage gain up to 2ⁿ at most. Here, VPC is suggested to realize a variable multiphase operation by changing the phase number p and topological path for the more suitable level of voltage gain so as to improve the power efficiency, especially for the lower output voltage Besides, PWM is adopted not only to enhance output regulation for different desired outputs, but also to reinforce output robustness to source/loading variation. Further, some theoretical analyses and designs include: n‐stage p‐phase MPSC model, steady‐state analysis, conversion ratio, power efficiency, output ripple, stability, capacitance selection, and control design. Finally, the closed‐loop MPSC is simulated, and the hardware is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

A single‐stage integrated bridgeless AC/DC converter for electrolytic capacitor‐less LED lighting applications

In this paper, a single‐stage integrated bridgeless AC/DC converter is proposed. As compared to its counterpart that is composed of totem‐pole boost power factor correction (PFC) cascade fly‐back DC/DC converter, the studied circuit has less components number while overcoming the limits of the totem‐pole type. Thus, it is suitable to the low‐power LED lighting applications. Furthermore, when both PFC inductors L_b and magmatic inductance L_m of the transformer TR1 operate at discontinuous current mode, the bus voltage v_CB can be used to decouple the ac input and constant dc output power. Thus, the approach of increasing bus voltage ripple is employed to eliminate electrolytic capacitors and obtain long operation lifetime. Additionally, it is able to be compatible with our studied twin‐bus configuration for increasing the overall efficiency. A 50‐W hardware prototype has been designed, fabricated, and tested in the laboratory to verify the proposed converter validity. Copyright © 2014 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

A single‐stage phase‐shifted full‐bridge AC/DC converter with variable frequency control

This letter presents a single‐stage soft‐switched full‐bridge AC/DC converter for low‐voltage/high‐current output applications. A phase‐shifted method with a variable frequency control is used to regulate the DC bus voltage and the output voltage of the single‐stage AC/DC converter. The proposed circuit topology and control scheme exhibit superior performances (i.e. high power factor, high‐efficiency, and ring‐free features). Correspondingly, a laboratory prototype, 500 W 5V/100A AC/DC converter, is implemented to verify the feasibility of the proposed design. Copyright © 2009 John Wiley & Sons, Ltd.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

A novel analog switch for high‐precision switched‐capacitor applications

The performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of ?81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.     

On the transposition of Gm–C filters to DC stabilized log‐domain filters

High‐order log‐domain filters could be designed by transposing the already known linear‐domain G_m–C filter topologies to the corresponding topologies in the log‐domain. This is achieved by using a non‐linear transconductor configuration, where the output current is exponentially related to its input and output voltages. A drawback of the non‐linear transconductor configuration already introduced in the literature is that a number of the transposed log‐domain filter topologies suffer from DC instability, while in some others a DC offset current appears at their output. In order to eliminate the aforementioned problems a modified non‐linear transconductor configuration for transposing G_m–C filter topologies to log‐domain filter topologies is introduced in this paper. The achieved improvements are demonstrated through a number of log‐domain filter configurations derived using the already introduced and the proposed transposition schemes. Copyright © 2006 John Wiley & Sons, Ltd.     

An interleaved high step‐up DC‐DC converter with double boost paths

This paper proposed a novel high step‐up converter with double boost paths. The circuit uses two switches and one double‐path voltage multiplier cell to own the double boost and interleaved effects simultaneously. The voltage gain ratio of the proposed DC‐DC converter can be three times the ratio of the conventional boost converter such that the voltage stress of the switch can be lower. The high step‐up performance is in accordance with only one double‐path voltage multiplier cell. Therefore, the number of diodes and capacitors in the proposed converter can be reduced. Furthermore, the interleaved property of the proposed circuit can reduce the losses in the rectifier diode and capacitor. The prototype circuit with 24‐V input voltage, 250‐V output voltage, and 150‐W output power is experimentally realized to verify the validity and effectiveness of the proposed converter. Copyright © 2014 John Wiley & Sons, Ltd.     

Dimmable integrated CMOS LED driver based on a resonant DC/DC hybrid‐switched capacitor converter

This paper presents a 7.7 ‐ mm² on‐chip LED driver based on a DC/DC resonant hybrid‐switched capacitor converter operating in the MHz range with and without output capacitor. The converter operation allows continuously dimming the LED while keeping control on both peak and average current. Also, it features no flickering even in the absence of output capacitor and for light dimmed down to 10% of the nominal value. The capacitors and switches of the LED driver are integrated on a single IC die fabricated in a low‐cost 5 V 0.18‐μm bulk CMOS technology. This LED driver uses a small (0.7 mm²) inductor of 100 nH, which is 10 times smaller value than prior art integrated inductive LED drivers, still showing a competitive peak efficiency of 93% and achieving a power density of 0.26 W/mm² (0.34 W/mm³).     

Design of a dual‐input SC DC–DC converter realizing negative outputs

Aimed at a back‐lighting application, a dual‐input switched‐capacitor (SC) DC–DC converter with battery charge process is proposed in this paper. The proposed converter can realize −1/N× (N = 2,3,…) step‐down conversion as well as (N + 1)/N× step‐up conversion. By converting clean energy such as solar energy, the proposed dual‐input converter not only drives light‐emitting diodes (LEDs) but also recharges the battery, although conventional single‐input converter only consumes battery energy. In the proposed converter, the −1/N× stepped‐down voltage is generated to drive the LED's cathode when the input voltage is insufficient to drive a 1× transfer mode. Furthermore, unlike conventional converters, the battery is charged by the (N + 1)/N× stepped‐up voltage when the LED back light is in standby mode. Hence, the proposed converter can realize long battery run time. The validity of circuit design is confirmed by theoretical analyses, simulations, and experiments. The derived theoretical formulas will be helpful to estimate circuit characteristics, because the theoretical results correspond well with the simulation program with integrated circuit emphasis (SPICE) simulation results. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Analytical synthesis of odd/even‐nth‐order elliptic Cauer filter structures using OTRAs

The operational transresistance amplifier (OTRA), the dual of the well‐known operational transconductance amplifier, is an attractive element for use in circuit design. One odd‐nth‐order and two even‐nth‐order OTRA‐R‐C or OTRA‐MOS‐C elliptic Cauer filter structures are presented using new analytical synthesis methods (ASMs). Because it is assumed in the synthesis procedure that the transresistance R_m → ∞, but in view of the fact that R_m is finite in practice, the more the number of OTRAs employed, the worse the precision of the output signals. By studying the sensitivity of the output to component variations, more precise output may be obtained by selecting one or two appropriate capacitance(s)/resistance(s) and adjusting their values suitably. H‐spice simulations are given to validate and demonstrate the theoretical predictions. Copyright © 2012 John Wiley & Sons, Ltd.     

A single‐stage high power‐factor bridgeless AC‐LED driver for lighting applications

An alternating‐current light‐emitting diode (AC‐LED) driver is implemented between the grid and lamp to eliminate the disadvantages of a directly grid‐tied AC‐LED lamp. In order to highlight the benefits of AC‐LED technology, a single‐stage converter with few components is adopted. A high power‐factor single‐stage bridgeless AC/AC converter is proposed with higher efficiency, greater power factor, less harmonics to pass IEC 61000‐3‐2 class C, and better regulation of output current. The brightness and flicker frequency issues caused by a low‐frequency sinusoidal input are surpassed by the implementation of a high‐frequency square‐wave output current. In addition, the characteristics of the proposed circuit are discussed and analyzed in order to design the AC‐LED driver. Finally, some simulation and experimental results are shown to verify this proposed scheme. Copyright © 2012 John Wiley & Sons, Ltd.     

Advanced power conditioner using sinewave modulated buck–boost converter cascaded polarity changing inverter

This paper presents an advanced power converter employs a sinusoidal voltage absolute value tracking buck–boost DC–DC converter in the first power processing stage and a polarity changing full-bridge inverter in the second stage. The proposed power conversion system has the capability of delivering good quantitative and qualitative sinusoidal output current and voltage waveforms with good output voltage regulation. Consequently, the complete voltage regulator system, which is mainly suitable for new energy generation systems as well as energy storage systems, can be constructed compactly and inexpensively without DC link electrolytic capacitor. Also, the paper presents an auxiliary passive resonant circuit for soft switching operation. Simulation results using PSIM software are presented to verify the operation principles and feasibility of the proposed power conversion system. Finally, these results are verified by means of an experimental prototype.     

Fault detection filter design for discrete‐time switched linear systems with mode‐dependent average dwell‐time

This paper is concerned with the problem of the fault detection (FD) filter design for discrete‐time switched linear systems with mode‐dependent average dwell‐time. The switching law is mode‐dependent and each subsystem has its own average dwell‐time. The FD filters are designed such that the augmented switched systems are asymptotically stable, and the residual signal generated by the filters achieves a weighted l₂‐gain for some disturbances and guarantees an H _? performance for the fault. By the aid of multiple Lyapunov functions combined with projection lemma, sufficient conditions for the design of the FD filters are formulated by linear matrix inequalities, furthermore, the filters gains are characterized in terms of the solution of a convex optimization problem. Finally, an application to boost convertor is given to illustrate the effectiveness and the applicability of the proposed design method. Copyright © 2013 John Wiley & Sons, Ltd.     

High‐power‐factor single‐switch AC to DC converter for LED lighting

In this paper, we report a novel single‐switch AC to DC step‐down converter suitable for light emitting diodes. The proposed topology has a buck and a buck–boost converter. The circuit is designed to operate in the discontinuous conduction mode in order to improve the power factor. In this topology, a part of the input power is connected to the load directly. This feature of the proposed topology increases the efficiency of power conversion, improves the input power factor, produces less voltage stress on intermediate stages, and reduces the output voltage in the absence of a step‐down transformer. The theoretical analysis, design procedure, and performance of the proposed converter are verified by simulation and experiment. A 36 V, 60 W prototype has been built to demonstrate the merits of this circuit. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Optimal switching Lyapunov‐based control of power electronic converters

This paper presents new ideas and insights towards a novel optimal control approach for power electronic converters. The so‐called stabilizing or Lyapunov‐based control paradigm is adopted, which is well known in the area of energy‐based control of power electronic converters, in which the control law takes a nonlinear state‐feedback form parameterized by a positive scalar λ . The first contribution is the extension to an optimal Lyapunov‐based control paradigm involving the specification of the optimal value for the parameter λ in a typical optimal control setting. The second contribution is the extension to more flexible optimal switching‐gain control laws, where the optimal switching surfaces are parameterized by a number of positive scalars λ _j . Systematic derivation of gradient information to apply gradient‐descent algorithms is provided. The proposed techniques are numerically evaluated using the exact switched model of a DC–DC boost converter. Copyright © 2016 John Wiley & Sons, Ltd.     

Performance analysis and calculation of critical inductance and output voltage ripple of a simple non‐isolated multi‐input bidirectional DC‐DC converter

In this paper, a simple non‐isolated multiple input (MI) bidirectional DC‐DC topology is proposed which can operate in buck, boost, or buck‐boost modes. The proposed topology utilizes a battery pack to realize the bidirectional power flow operation especially when the input sources are non‐storable ones. The excess energy of input sources can be stored in the battery and be injected to the load, when required. Simultaneous or independent power transfer of input sources is also provided. For better evaluation, the proposed topology has been compared with several recently presented novel topologies, from view point of number of inductors, capacitors, switches, and diodes. Comparison results show that the proposed topology utilizes less number of components (switches, inductors, capacitors, and current sensors) which can reduce the size, cost, and complexity of converter. Different operational modes of the proposed topology (unidirectional buck, boost, buck‐boost modes, and bidirectional mode) have been presented. Also, boost mode of the proposed topology has been investigated in detail, from design point of view, and generalized relationships have been proposed for calculation of critical inductance (CI) and output voltage ripple (OVR) of proposed n‐input boost topology. To validate proposed theoretical concepts, the proposed topology has been modeled and simulated in PSCAD/EMTDC software, and the 3‐input boost version has been experimentally implemented. Simulation and experimental results confirm appropriate performance of the proposed topology.