Evaluation of standard impulse voltage/current measuring systems in Japan

A national‐standard‐class impulse voltage measuring system in Japan was developed in the consignment research of the Ministry of Economy, Trade and Industry (METI) and New Energy and Industrial Technology Development Organization (NEDO) from 1998 to 2006. The standard measuring system for the impulse voltage measurements is managed by the Japan High Voltage Impulse Testing Laboratories Liaison (JHILL) established under the Japan Electric Machine Industry Association (JEMA). The standard impulse voltage measuring system calibrates other measuring systems and assesses their uncertainties, and, therefore, its uncertainty needs to be evaluated independently. The principal components of the system are a voltage divider, a digital recorder, and a low‐voltage calibrator which generates impulse voltages of known peak voltages and waveforms. Moreover, a reference measuring system for impulse current in Japan was also developed in 2009 supported by JEMA. Its international compatibility was confirmed through an international comparison test. Through domestic comparison tests, traceability among transducers of impulse current in Japan was established. In this paper, the constitution of these measuring systems, their performance, and related latest activities, such as comparison tests, are described. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Test circuit of impulse spark‐over voltage with different rates of rise for gas discharge tubes

The impulse spark‐over voltage of the gas discharge tube (GDT) is strongly related to the rate of rise (RoR) of the voltage. At present, due to the convenience of the test instrument, conventional impulse waveforms, such as 1.2/50 and 10/700 μs, are often adopted to conduct such kind of test for GDT. It has been found that these waveforms are able to generate valid waveforms only with limited RoRs and relatively narrow valid voltage ranges. This paper deals with a simple series RC circuit to test the GDT's impulse spark‐over voltage using a ramp voltage, which is approached by an initial portion of a steeply rising voltage impulse whose normal peak value is several times the breakdown voltage of the GDT. The basic circuit theory is described, and the RoR of the output voltage is correlated with the circuit parameters. Moreover, the series RC circuit in this paper is found to be able to deliver a ramp voltage with more consistent RoR than an RLC circuit. The results in this paper provide some suggestions for the revision of relevant standards (e.g., ITU‐T K.12 and IEC 61643‐311). Circuit parameters for different RoRs ranging from 100 V/μs to 1 kV/ns are also established. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

我国大规模可再生能源基地与技术的发展研究

从可持续发展看,化石能源终将耗竭.二十一世纪上半叶,能源结构的调整过程已经开始,需要发展大规模非水能的可再生能源,主要是风能、太阳能与生物质能,并大力推进荒漠地区基地和氢能的发展.中国科学院学部组织有关院士及专家进行了我国大规模可再生能源基地与技术的发展研究.本文简要叙述了有关结论与建议.     

标准冲击电压校准器的研制与溯源

冲击电压测试设备及仪器需要进行校准以保证冲击电压试验结果的准确性,为此研制了一种校准冲击电压测试设备仪器的冲击电压校准器。在介绍了设计原理后进行了不确定度分析和量值溯源。校准器的电压量程范围为30～1000V,能产生满足IEC60060-1:1989的标准雷电和操作冲击波,并且通过高精度直流电压源以及组成冲击回路的高精度、高稳定度的电感、电容、电阻等基本元器件,从而将冲击电压的参数经过这些元件的不确定度传递到相应的直流电压标准及元件标准上去。经过不确定度来源的分析和评估,校准器所产生冲击电压峰值的不确定度为0.05%,时间参数的不确定度<0.5%,可作为校准冲击电压测试设备以及仪器的标准波源。     

电磁兼容性测试用冲击电压分压器设计及实现

基于"场-路"耦合的思想,通过电磁场仿真计算提取电阻分压器的杂散参数,建立了冲击电压下电阻分压器的等效电路模型,进而研究了电阻分压器结构参数对测量结果的影响.依据仿真分析结果,设计并实现了电磁兼容性测试用10kV冲击电压分压器与冲击电压测量系统.经测试该系统测量冲击电压峰值的扩展不确定度、测量波前时间的扩展不确定度、测量半波时间的扩展不确定度等,均满足电磁兼容性测量要求.     

Dielectric characteristics of oil‐filled transformer in the presence of nonstandard lightning surge waveforms

To achieve a rational insulation design for transformers, it is important to evaluate dielectric strength against surges actually impinging on equipment on‐site. This paper deals with the breakdown voltage characteristics of an oil gap under nonstandard lightning surge waveforms combined with oscillatory voltages. It is found that the breakdown voltages of the oil gap under nonstandard impulse waveforms are higher than standard lightning impulse voltages. The results can be ascribed to V–t characteristics of the oil gap in short‐time impulse voltage ranges. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 146(3): 39–45, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10229     

一种数字化冲击电压波形重构新算法

为减少数字化冲击测量系统的测量误差,分析了冲击电压经数字化冲击测量系统后被测波形产生畸变的原因;提出了一种利用离散Gabor变换展开去噪与增量维纳滤波器相结合的冲击电压波形重构算法。IEC1083-2测试数据发生器产生的波形信号的研究表明,该法可有效去除噪声,波形复原准确度和稳定性较高。     

A soft‐switching high step‐up DC‐DC converter with a single magnetic component

A soft‐switching high step‐up DC‐DC converter with a single magnetic component is presented in this paper. The proposed converter can provide high voltage gain with a relatively low turn ratio of a transformer. Voltage doubler structure is selected for the output stage. Due to this structure, the voltage gain can be increased, and the voltage stresses of output diodes are clamped as the output voltage. Moreover, the output diode currents are controlled by a leakage inductance of a transformer, and the reverse‐recovery loss of the output diodes is significantly reduced. Two power switches in the proposed converter can operate with soft‐switching due to the reflected secondary current. The voltages across the power switches are confined to the clamping capacitor voltage. Steady‐state analysis, simulation, and experimental results for the proposed converter are presented to validate the feasibility and the performance of the proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.     

冲击电阻分压器响应特性的研究

笔者研制了500 kV精密冲击电阻分压器,用于测量冲击全波及波前截波.笔者使用ATP软件对冲击电阻分压器进行了电路仿真,并且利用纳秒方波源对其进行了阶跃波响应试验,通过改变阻尼电阻大小、高压臂阻值及高压臂距离地面高度,研究了影响冲击电阻分压器响应特性的因素.所研制的分压器样机部分响应时间为7.4 ns,过冲18.8％.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and implementation of a high step‐up converter for fuel cell power‐generation systems

This paper presents a high step‐up converter, which utilizes a three‐winding coupled inductor and a rectified voltage‐doubler circuit to obtain high step‐up gain for fuel cells. The proposed converter functions as an active‐clamp circuit, which relieves large voltage spikes across the power switches. Thus, power switches with low‐voltage‐rated can be utilized to reduce conduction losses and circuit cost. Energy stored in leakage inductances of the coupled inductor is recycled to the output terminal, resulting in efficiency improvements. In addition, the coupled inductor in the presented converter can also have extra windings in order to achieve higher voltage gain. Finally, a prototype circuit with an input voltage of 60 V and an output voltage of 380 V is developed for a 1000 W‐rated fuel cell power‐generation system to validate its performance, and experimental waveforms and measured efficiency under different input voltages and output power level are demonstrated. Copyright © 2016 John Wiley & Sons, Ltd.     

A quad‐band W‐CDMA transceiver IC–direct conversion architecture with fractional frequency divider

A quad‐band (0.8, 1.7, 2, and 1.4 GHz) wideband code division multiple access (W‐CDMA) transceiver, which uses a divide‐by‐2.5 frequency divider in local parts of a direct‐conversion architecture, has been developed. Using the fractional‐2.5 frequency divider reduces the fractional bandwidth of the voltage‐controlled oscillator and avoids injection locking of the local RF synthesizer perfectly. This transceiver achieved 3% error‐vector magnitude and—46 dB ACLR, which satisfy the margin given in standard specifications. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Analysis and evaluation of waveform parameters for oscillating impulse voltage

This paper describes the effect of residual inductance of the impulse generator circuit. The analysis of waveform and the evaluation of waveform parameters were made for an oscillating lightning impulse. The peak value (overshoot factor or k‐factor), oscillation frequency, 30% value, 90% value, time to half‐value, and virtual origin are derived from the solution of third‐order derivative equation of the equivalent circuit. The comparison with the oscillating and standard lightning impulse was made. Also, the effects on overshoot, front time and the load‐side capacitance are theoretically clarified. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

1‐V continuous‐time equalizers for multi‐gigabit short‐haul optical fiber communications

Two new CMOS analog continuous‐time equalizers for high‐speed short‐haul optical fiber communications are presented in this paper. The proposed structures compensate the limited bandwidth‐length product of 1‐mm step‐index polymer optical fiber channels (45 MHz, 100 m) and have been designed in a standard 0.18‐µm CMOS process. The equalizers are aimed for multi‐gigabit short‐range applications, targeting up to 2 Gb/s through a 50‐m step‐index polymer optical fiber. The prototypes operate with a single supply voltage of only 1 V and overcome the severe limitations suffered by the widely used degenerated differential pair caused by the low supply voltage. Copyright © 2012 John Wiley & Sons, Ltd.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

Non‐isolated large step‐down voltage conversion ratio converter with non‐pulsating output current

A non‐isolated dual half‐bridge large step‐down voltage conversion ratio converter with non‐pulsating output current, utilizing one coupled inductor, one energy‐transferring capacitor, and one output inductor, is presented herein. The coupled inductor is connected between the input voltage and the output inductor and plays a role to step down the input voltage. Furthermore, the output inductor is used not only to further step down the voltage but also to provide a non‐pulsating output current. Moreover, the proposed converter can achieve zero‐voltage switching. In this study, detailed theoretical deductions and some experimental results of a prototype with 48 V input voltage, 3.3 V output voltage, and 10 A output current are provided to demonstrate the feasibility and effectiveness of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd.     

冲击电压分压器线性度试验研究

冲击电压测量系统在溯源过程中通常使用低压直流源或冲击电压校准器测量分压器的刻度因数,因而必须考虑分压器线性度对测量系统测量不确定度的影响问题。在现今我国尚未建立标准系统的情况下,提出用试验的方法测量分压器的线性度:首先用线性度可忽略的电阻分压器R200S得到冲击电压发生器的线性度,采用直流分压器测量冲击电压发生器的充电电压,测量试品分压器HCR600示值与充电电压的比值,修正发生器的影响后得到分压器的线性度,结果显示HCR600的线性度单调下降,从+0.4%至-0.8%,正负极性最大差值为0.14%,且负极性的线性度优于正极性。然后进行试验验证:用线性度已知的500kV电阻分压器与HCR 600进行比对而得到线性度变化曲线,并与之前的试验结果进行比较,两者变化趋势相同,相同电压下最大差值点仅为0.15%。说明此方法可较准确地测量分压器的线性度,可用于冲击电压建标时的试验验证,发生器等试验设备满足一定条件时此方法也可用于特高压冲击设备的校准。     

Analysis and design of a ZVS converter for high voltage input–low voltage output application

This paper proposes a full‐bridge (d = 50%) cascaded buck topology which is a very suitable circuit for high voltage input–low voltage output applications with high output current. Benefiting from working under a large duty cycle, the proposed converter can easily achieve zero voltage switching turn‐on and turn‐off of active switches in a full bridge. Small‐signal model of this topology is analyzed through its corresponding peak current mode control. Its small‐signal transfer function is given, and the control loop design is discussed. Advantages of this topology and operation principles are analyzed. Design guidelines, drawn from this analysis, are applied on a low‐voltage (3.3 V) output voltage prototype to validate the proposed concept. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A very low complexity IR‐UWB transmitter with BPSK modulation for balanced antenna

A very low complexity impulse radio‐ultrawideband (IR‐UWB) transmitter suitable for balanced antenna is presented. This all‐digital transmitter employs the binary phase‐shift keying (BPSK) modulation scheme and eliminates the need for a balun. Also, a new Gaussian monocycle pulse generator is proposed which is used as impulse transmitted signal. The transmitter circuit was designed in 0.18‐μm complementary metal–oxide–semiconductor technology. The post‐simulation results show that the core chip size was only 0.02 mm². The output amplitude pulse yielded 150 mV peak‐to‐peak under a supply voltage of 1.8 V. Simulation results show that the transmitter consumes 8.5 pJ/pulse for 200‐MHz pulse repeating frequency. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.