Si/Si1-x-yGexCy/Si heterojunctionbipolar transistors

We report the first Si/Si_1-x-yGe_xC_y /Si n-p-n heterojunction bipolar transistors and the first electrical bandgap measurements of strained Si_1-x-yGe_x C_y on Si (100) substrates. The carbon compositions were measured by the shift between the Si_1-x-yGe_xC_y and Si_1-xGe_x X-ray diffraction peaks. The temperature dependence of the HBT collector current demonstrates that carbon causes a shift in bandgap of +26 meV/%C for germanium fractions of x=0.2 and x=0.25. These results show that carbon reduces the strain in Si_1-x Ge_x at a faster rate than it increases the bandgap (compared to reducing x in Si_1-xGe_x), so that a Si _1-x-yGe_xC_y film will have less strain than a Si_1-xGe_x film with the same bandgap     

Si/Si1-xGex heterojunction bipolartransistors produced by limited reaction processing

Si/Si_1-xGe_x heterojunction transistors (HBTs) fabricated by a chemical vapor deposition (CVD) technique are reported. A rapid thermal CVD limited-reaction processing (LRP) technique was used for the in situ growth of all three device layers, including a 20-mm Si_1-xGe_x layer in the base. The highest current gains observed (β=400) were for a Si/Si_1-x Ge_x HBT with a base doping of 7×10¹⁸ cm^-3 near the junction and a shallow arsenic implant to form ohmic contacts and increase current gain. Ideal base currents were observed for over six decades of current and the collector current remained ideal for nearly nine current decades starting at 1 pA. The bandgap difference between a p-type Si layer doped to 5×10¹⁷ cm^-3 and the Si_1-xGe_x(x=0.31) base measured 0.27 eV. This value was deduced from the measurements of the temperature dependence of the base current and is in good agreement with published calculations for strained Si_1-xGe_x layers on Si     

Photoresponse model for Si1-xGex/Siheterojunction internal photoemission infrared detector

A photoresponse model has been developed for the Si_1-xGe_x/Si heterojunction internal photoemission (HIP) infrared detector at wavelengths corresponding to photon energies less than the Fermi energy. A Si_0.7Ge_0.3/Si HIP detector with a cutoff wavelength of 23 μm and an emission coefficient of 0.4 eV^-1 has been demonstrated. The model agrees with the measured detector response at λ>8 μm. The potential barrier determined by the model is in close agreement (difference ~4 meV) with the potential barrier determined by the Richardson plot, compared to the discrepancies of 20-50 meV usually observed for PtSi Schottky detectors     

The scaled performance of Si/Si1-xGexresonant tunneling diodes

Small area resonant tunneling diodes (RTDs) with strained Si_0.4Ge_0.6 potential barriers and a strained Si quantum well grown on a relaxed Si_0.8Ge_0.2 virtual substrate were fabricated and characterized. A room temperature peak current density (J_P) of 282 kA/cm² with a peak to valley current ratio (PVCR) of 2.43 were recorded for a 5×5 μm ² sample, the highest values reported to date for Si/Si_1-xGe_x RTDs. Scaling of the device size demonstrated a decrease in J_P proportional to an increase in the lateral area of the tunnel junctions, whereas the PVCR remained approximately constant. This observation suggests that the dc behavior of such Si/Si_1-xGe_x RTD design is presently limited by thermal effects     

High performance Si/Si1-xGex resonanttunneling diodes

Resonant tunneling diodes (RTDs) with strained i-Si_0.4Ge_0.6 potential barriers and a strained i-Si quantum well, all on a relaxed Si_0.8Ge_0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm² at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si_1-xGe_x RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si_1-xGe_x heterojunction field effect transistor based integrated circuits     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

Low- and high-field electron-transport parameters for unstrainedand strained Si1-xGex

Ohmic minority and majority drift mobilities as well as saturation velocities are reported for unstrained and strained Si_1-xGe _x alloys up to z=0.31. The electron-transport model is verified by measurements of the in-plane majority drift mobility in strained Si_1-xGe_x samples for various dopant and Ge concentrations. Saturation velocities are determined by full-band Monte Carlo simulations. There is no substantial decrease in the mobility perpendicular to the Si/SiGe interface for doping concentrations above 10¹⁹ cm^-3 and growing x. In contrast, the saturation-drift velocity is strongly reduced with x     

Strained n-Channel Transistors With Silicon Source and Drain Regions and Embedded Silicon/Germanium as Strain-Transfer Structure

We report the demonstration of 55 nm gate length strained n-channel field-effect transistors (n-FETs) having an embedded Si_1-xGe_x structure that is beneath the Si channel region and which acts as a strain-transfer structure (STS). The Si_1-xGe_x STS has lattice interactions with both the silicon source and drain regions and with the overlying Si channel region. This effectively results in a transfer of lateral tensile strain to the Si channel region for electron mobility enhancement. The mechanism of strain transfer is explained. Significant drive current I_on enhancement of 18% at a fixed off-state leakage I_off of 100 nA/mum is achieved, which is attributed to the strain-induced mobility enhancement. Furthermore, continuous downsizing of transistors leads to higher I_on enhancement in the strained n-FETs, which is consistent with the increasing transconductance G_m improvement when the gate length is reduced.     

Heterojunction bipolar transistors using Si-Ge alloys

Advanced epitaxial growth techniques permit the use of pseudomorphic Si_1-xGe_x alloys in silicon technology. The smaller bandgap of these alloys allows for a variety of novel band-engineered structures that promise to enhance silicon-based technology significantly. The authors discuss the growth and properties of pseudomorphic Si_1-xGe_x structures and then focus on their applications, especially the Si_1-xGe_x -base heterojunction bipolar transistor (HBT). They show that HBTs in the Si_1-xGe_x system allow for the decoupling of current gain and intrinsic base resistance. Such devices can be made by using a variety of techniques, including molecular-beam epitaxy and chemical vapor deposition. The authors describe the evolution of fabrication schemes for such HBTs and describe the DC and AC results obtained. They show that optimally designed HBTs coupled with advanced bipolar structures can provide performance leverage     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications     

Low-resistance bandgap-engineeredW/Si1-xGex/Si contacts

Bandgap-engineered W/Si_1-xGe_x/Si junctions (p⁺ and n⁺) with ultra-low contact resistivity and low leakage have been fabricated and characterized. The junctions are formed via outdiffusion from a selectively deposited Si_0.7Ge _0.3 layer which is implanted and annealed using RTA. The Si _1-xGe_x layer can then be selectively thinned using NH₄OH/H₂O₂/H₂O at 75°C with little change in characteristics or left as-deposited. Leakage currents were better than 1.6×10^-9 A/cm² (areal), 7.45×10^-12 A/cm (peripheral) for p⁺/n and 3.5×10^-10 A/cm² (peripheral) for n⁺/p. W contacts were formed using selective LPCVD on Si_1-xGe_x. A specific contact resistivity of better than 3.2×10^-8 Ω cm² for p ⁺/n and 2.2×10^-8 Ω cm² for n⁺/p is demonstrated-an order of magnitude n⁺ better than current TiSi₂ technology. W/Si_1-xGe _x/Si junctions show great potential for ULSI applications     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

Numerical simulation and comparison of Si BJTs andSi1-xGex HBTs

Using the Monte Carlo method for the solution of the Boltzmann transport equation, the authors analyze the low-field carrier mobilities of strained layer and bulk Si and Si_1-xGe_x alloys. Strained alloy layers exhibit higher low-field mobility compared with bulk Si at doping levels >10¹⁸ cm^-3 and for a Ge mole fraction x⩽0.2, while the unstrained alloy bulk low-field mobility is always lower than that of Si for any doping level or mole fraction. These mobilities are then used in a two-dimensional drift-diffusion equation solver to simulate the performance of Si BJTs (bipolar junction transistors) and Si_1-xGe_x HBTs (heterojunction bipolar transistors). The substitution of a Si_0.8 Ge_0.2 layer for the base region leads to a significant improvement in current gain, turn-on voltage, and high-frequency performance. Maximum unity current gain frequency f_T increases two times over that of an Si BJT if the bulk alloy mobility is used for the alloy base layer; it increases three times if strained-layer mobility is used. Maximum frequency of oscillation also improves, but not as dramatically as f_T     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

Improved low temperature characteristics of P-channel MOSFETs withSi1-xGex raised source and drain

P-channel metal-oxide-semiconductor field-effect transistors with Si_1-xGe_x raised source and drain (RSD) have been fabricated and further studied for low temperature applications. The Si _1-xGe_x RSD layer was selectively grown by ANELVA SRE-612 ultra-high vacuum chemical vapor deposition (UHVCVD) system. Compared to devices with conventional Si RSD, improved transconductance and specific contact resistance were obtained, and these improvements become even more dramatic with reducing channel length. Well-behaved short channel characteristics with reduced drain-induced barrier lowering (DIBL) and off-state leakage current are demonstrated on devices with 100 nm Si_1-xGe_x RSD, due to the resultant shallow junction and less implantation damage. Moreover, temperature measurements reveal that Si_1-xGe_x RSD devices show more dramatic improvement in device performance at low temperature (-50 °C) operation, which can be ascribed to the higher temperature sensitivity of the Si_1-xGe_x sheet resistance     

Electron drift mobility model for devices based on unstrained andcoherently strained Si1-xGex grown on <001>silicon substrate

The electron drift mobility for unstrained and coherently strained Si_1-xGe_x grown on a <001> silicon substrate is analytically obtained for Ge fractions less than 30%. The method is based on the following two assumptions: the conduction bands of the unstrained alloy are Si-like for Ge fraction less than 30%, and in the case of the coherently strained alloy, strain-induced energy shifts occur in the conduction band valleys. The shifts in energy yield two different mobility values: one corresponding to the growth plane with a value larger than the unstrained mobility, and the other parallel to the growth direction and correspondingly smaller in value. In comparison to silicon, the results show a degradation of both the unstrained mobilities for doping levels up to 10¹⁷ cm^-3. Beyond this doping level, the strained mobility component parallel to the growth direction becomes slightly larger than the mobility of silicon     

Gate Influence on the Layout Sensitivity of $ hbox{Si}_{1 - x}hbox{Ge}_{x} hbox{S/D}$ and $hbox{Si}_{1 - y}hbox{C}_{y} hbox{S/D}$ Transistors Including an Analytical Model

We present a simulation study on the effect of the gate module on the channel stress in Si_1-xGe_x and Si_1-yC_y S/D MOS transistors. Stiff gate materials, such as titanium nitride, lead to a decreased channel stress, while a replacement-gate scheme allows the increase of the effectiveness of the Si_1-xGe_x and Si_1-yC_y S/D techniques significantly, independent of the gate material used. The drawback of using a replacement gate is that the channel stress becomes more sensitive to layout variations. In terms of effect on Si_1-xGe_x/Si_1-yC_y S/D stress generation, using a thin metal gate capped by polysilicon is similar to a full metal gate if the thin metal gate thickness exceeds 10 nm. Even metal gates as thin as 1 nm have a clear influence on the stress generation by Si_1-xGe_x/Si_1-yC_y S/D. Removing and redepositing the polysilicon layer while leaving the underlying metal gate unchanged increases the stress, although not to the same extent as for complete gate removal. A simple analytical model that estimates the stress in nested short-channel Si_1-xGe_x and Si_1-yC_y S/D transistors is presented. This model includes the effect of germanium/carbon concentration, active-area length, as well as the effect of gate length and the Young's modulus of the gate. Good qualitative agreement with 2-D finite element modeling is demonstrated.     

Suppression of boron penetration in p-channel MOSFETs usingpolycrystalline Si1-x-yGexCy gatelayers

Boron penetration through thin gate oxides in p-channel MOSFETs with heavily boron-doped gates causes undesirable positive threshold voltage shifts. P-channel MOSFETs with polycrystalline Si_1-x-yGe_xC_y gate layers at the gate-oxide interface show substantially reduced boron penetration and increased threshold voltage stability compared to devices with all poly Si gates or with poly Si_1-xGe gate layers. Boron accumulates in the poly Si_1-x-yGe_xC_y layers in the gate, with less boron entering the gate oxide and substrate. The boron in the poly Si_1-x-yGe_xC_y appears to be electrically active, providing similar device performance compared to the poly Si or poly Si_1-xGe_x gated devices     

Low-temperature annealing of polycrystallineSi1-xGex after dopant implantation

Hall effect measurement was employed to study the isothermal annealing of boron or phosphorus implanted polycrystalline Si_1-x Ge_x thin films, with x varying from 0.3-0.55. X-ray diffraction and cross-sectional transmission electron microscopy were used to study the crystal structure, whereas X-ray photoelectron spectroscopy was used to determine the film composition and the chemical bonding states of the elements. In low-temperature (⩽600°C) annealing, the conductivity, the dopant activation, and the Hall effect mobility decreased during extended annealing. The effective activation of phosphorus was less than 20% and decreased with increasing Ge content. Boron activation could reach above 70%. It was also found that Si_1-xGe_x could be oxidized at 600°C in a conventional furnace even with N₂ protection, especially for phosphorus doped films with high Ge content. Consequently, a low-temperature SiO₂ capping layer is necessary during extended annealing