Space Charges Effect of Static Induction Transistor

The space charge effect (SCE) of static induction transistor (SIT) that occurs in high current region is systematically studied.The I-V equations are deduced and well agree with experimental results.Two kinds of barriers are presented in SIT,corresponding to channel voltage barrier control (CVBC) mechanism and space charge limited control (SCLC) mechanism respectively.With the increase of drain voltage,the gradual transferring of operational mechanism from CVBC to SCLC is demonstrated.It points out that CVBC mechanism and its contest relationship with space charge barrier makes the SIT distinctly differentiated from JFET and triode devices,etc.The contest relationship of the two potential barriers also results in three different working regions,which are distinctly marked and analyzed.Furthermore,the extreme importance of grid voltage on SCE is illustrated.     

Fine-Grain Sleep Transistor Insertion for Leakage Reduction

首先给出一种泄漏电流和延时的简化模型,并且在此基础上提出了一种降低泄漏电流的细粒度休眠晶体管插入法.该方法的核心是利用混合整数线性规划方法同时确定插入细粒度休眠晶体管的位置和尺寸.从实验结果可以发现,由于这种方法更好地利用了电路中的延时余量,所以在电路性能不受影响的情况下可以减小79.75%的泄漏电流;并且在一定范围内放宽电路的延时约束可以更大幅度地降低泄漏电流.与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积.     

The 3DA511 Pulsed Power Transistor

The 3DA511 device is a high pwoer transistor designed for L-band pulsed output and drive applications.     

Perturbation-Based Fourier Series Analysis of Transistor Amplifier

A perturbation-based Fourier series model is proposed to approximate the nonlinear distortion in weakly nonlinear circuits. This general model is applicable to any set of multi-variable state equations that completely describe a nonlinear circuit. This model is applied to a common emitter amplifier circuit wherein the transistor is represented by Ebers–Moll nonlinear current equations. Appropriate state variables are defined, then the linear and nonlinear parts of the Ebers–Moll current equations are separated, and a small perturbation parameter is incorporated into the nonlinear part. Now these current equations are incorporated into the set of KCL, KVL equations defined for the circuit and the state variables are perturbatively expanded. Hence, multi-variable state equations are obtained from these equations. The state variables are approximated up to first order through Fourier series expansion, as described in the proposed model. The main advantage of the proposed model is that it is simple and straightforward approach to analyze weakly nonlinear circuits, as it involves matrix computations and the calculations of exponential Fourier coefficients.     

A 162GHz Self-Aligned InP/InGaAs Heterojunction Bipolar Transistor

报道了发射极自对准的InP基异质结双极型晶体管.在集电极电流Ic=34.2mA的条件下,发射极面积为0.8μm×12μm的InP HBT截止频率fT为162GHz,最大振荡频率fmax为52GHz,最大直流增益为120,偏移电压为0.10V,击穿电压BVCEO达到3.8V(Ic=0.1μA).这种器件非常适合在高速低功耗方面的应用,例如OEIC接收机以及模拟数字转换器.     

The Bipolar Field-Effect Transistor:XⅢ. Physical Realizations of the Transistor and Circuits(One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its onetransistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick,pure and impure base,with electron and hole contacts,and the corresponding theoretical current–voltage characteristics previously computed by us,without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base trans...     

A Very Fast Method for the DC Analysis of Diode–Transistor Circuits

The paper offers a universal method for finding a unique or multiple DC operating points of nonlinear circuits. The developed method is based on the theory known as a linear complementarity problem (LCP) and the homotopy concept. It is a combination of Lemke’s method for solving LCP and some variant of the homotopy method. To express the problem of finding DC operating points in terms of LCP, an appropriate piecewise–linear approximation of diode characteristic is proposed. Although the method does not guarantee finding all the DC operating points, usually it finds them. The method is very fast and remarkably efficient. Numerical examples, including practical BJT and CMOS circuits having a unique or multiple DC operating points are given.     

Compact Analytical Model of Double Gate Junction-less Field Effect Transistor Comprising Quantum-Mechanical Effect

We investigate the quantum-mechanical effects on the electrical properties of the double-gate junctionless field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.     

Frequency Variations of π-equivalent Circuit Parameters of a Junction Transistor †

One of the most useful small-signal equivalent circuit representations is based on a m-equivalent circuit representation of the transistor in a common-emitter connection. This m-equivalent circuit representation is more readily and commonly employed in circuit analysis or design in comparison with a ^'-equivalent circuit representation. The variation of equivalent circuit parameters at high frequencies in the π-equivalent circuit representation was determined by Giacoletto experimentally. Unfortunately, however, we have no example but the above, in spite of this problem being very common and important. The exact expression for π-equivalent circuit parameters is too complicated to be calculated. The result may be somewhat simplified by expanding the hyperbolic function into a Taylor series and retaining only the first few terms. Numerical values of these approximate expressions are calculated and then compared with values calculated from the corresponding exact expression. Furthermore, w-equivalent circuit parameters relative to low-frequency values are given as a function of frequency relative to f_T and f_α. The π-equivalent circuit parameters of a p-n-p germanium alloy-junction transistor of the diffusion (homogeneous base) type are obtained by measuring small-signal h parameters under the low-level injection conditions with an impedance bridge. Then, it is made clear that they are in reasonably good agreement with theoretical values. The approximate expression for α is proposed, where α is analysed in terms of magnitude and phase shift. It is shown that it is more exact and more useful than the expressions such as the Thomas-Moll expression, etc., as a result of discussing the errors in the approximations of the equations.     

High Performance 20nm GaSb/InAs Junctionless Tunnel Field Effect Transistor for Low Power Supply

We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10-17A/ m, ION of 9 A/ m, ION/IOFF of 1×1011,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.     

The Bipolar Field-Effect Transistor: Ⅷ. Longitudinal Gradient of Longitudinal Electric Field (Two-MOS-Gates on Pure-Base)

This paper evaluates the electric current terms from the longitudinal gradient of the longitudinal electric field in Bipolar Field-Effect-Transistors (BiFETs) with a pure base and two MOS gates operating in the unipolar (elec-tron) current mode. These nMOS-BiFETs, known as nMOS-FinFETs, usually have electrically short channels compared with their intrinsic Debye length of about 25 μm at room temperatures. These longitudinal electric current terms are important short-channel current components, which have been neglected in the computation of the long-channel elec-trical characteristics. This paper shows that the long-channel electrical characteristics are substantially modified by the longitudinal electrical current terms when the physical channel length is less than 100 nm.     

Silicon Metal–Oxide–Semiconductor Transistor with a Dependent Pocket Contact and Two-Layer Polysilicon Gate

Semiconductors - The characteristics of two design-technology versions of a silicon metal–oxide–semiconductor (MOS) silicon on insulator (SOI) transistor with a source-aligned substrate...     

Design and Simulation of a Light-Activated Darlington Transistor Based on a SiCGe/3C-SiC Hetero-Structure

针对抗电磁干扰的需要提出了一种由SiCGe/3C-SiC异质结构成的光控达林顿晶体管设计.用多维器件模拟软件ISE对这种新型功率开关进行了特性仿真.结果表明,与采用其他结晶类型的碳化硅衬底相比,SiCGe与3C-SiC间较小的晶格失配有利于提高器件性能,可使其最大共射极电流增益达到890,获得最好的光触发特性和较好的Ⅰ-Ⅴ特性,饱和压降大约为4V.     

The Bipolar Field-Effect Transistor:Ⅶ. The Unipolar Current Mode for Analog-RF Operation(Two-MOS-Gates on Pure-Base

This paper reports the DC steady-state current-voltage and conductance-voltage characteristics of a Bipolar Field-Effect Transistor (BiFET) under the unipolar (electron) current mode of operation, with bipolar (elec-tron and hole) charge distributions considered. The model BiFET example presented has two MOS-gates on the two surfaces of a thin pure silicon base layer with electron and hole contacts on both edges of the thin base. The hole contacts on both edges of the thin pure base layer are grounded to give zero hole current. This 1-transistor analog-RF Basic Building Block nMOS amplifier circuit, operated in the unipolar current mode, complements the 1-transistor digital Basic Build Block CMOS voltage inverter circuit, operated in the bipolar-current mode just presented by us.     

Simulation and Analysis of Photo—charge Transfer Characteristics of Bipolar Junction Photogate Transistor for CMOS Imagers

The principle of the two carriers contributing to carry the pixel signal charges is firstly presented,and then the bipolar junction photogate transistor(BJPT)with high performance is proposed for the CMOS image sensor.The numerical analytical model of the photo-Chrge transfer for the bipolar junction photogate is established in detail.Some numerical simulations are obtained unider 0.6μm CMOS process,which show that its readout rate increases exponentially with the increase of the photo-Charge at applied voltage.     

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeO _x )-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.     

Improvements on the Voltage Resistant Capability and Ⅰ-Ⅴ Characteristics of Static Induction Transistor with Buried Gate Structure

静电感应晶体管(SIT)有源区外围边界各种寄生电流的存在,不仅造成了阻断态下漏电增大,导致Ⅰ-Ⅴ特性异常,造成器件性能劣化,并且降低了器件的成品率.在器件有源区周围设计了保护沟槽,形成了槽台结构的孤岛,从物理上有效地切断了可能的寄生电流,改善了器件的耐压能力,优化了Ⅰ-Ⅴ特性.槽台结构通过对表面的台面造型来控制表面电场,能有效提高器件的击穿电压,改善器件电性能.     

A Novel Dual-Modulus 2.8 GHz Divide-by-127/128 Prescaler Using Pull Down Transistor in 0.35 μ m CMOS Technology

Design of high divide-by-value dual-modulus prescaler remains a challenge in CMOS realization for high speed operation. Prior arts for dual modulus prescaler either divide by a low divide-by-value or cannot operate at high speed. The proposed topology is suitable for high divide-by-value operation at high speed.