The role of buffer layer in strontium bismuth tantalate based ferroelectric gate mos structures for non-volatile non destructive read out memory applications

Abstract

Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO₂) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO₂ film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric-metal (MFM) structures with various SBT film thickness’ were also studied.     

(Zr/Ti) ratio effect on RF magnetron sputtered lead titanate zirconate films

Abstract

Sputtered Pb(Zr_xTi_1?x)O₃ thin films with various (Zr/Ti) compositions ranging from 15/85 to 70/30 were grown and characterised in terms of structural and electrical properties. PZT thin films, with 0.7–0.8μm thickness, were deposited on Si/SiO₂/Ti/Pt by sputtering followed by conventional annealing. The sputtering conditions were the same for all the compositions. There were no apparent differences in crystallographic orientation as a function of Zr/Ti and the films a-lattice constant evolution is not exactly identical to the one of bulk ceramics. The permittivity increases when the Zr concentration increases and decreases just after the mor-photropic composition i.e. Zr-rich films. The ferroelectric properties are very sensitive to the Zr/Ti ratio. For example, the coercive field increases when the Ti concentration in the film increases.     

Improvement of Dielectric and Interface Properties of CeO2 Buffer Layer by Using the Metal Seed Layer and N2 Plasma Treatment

In this paper, we investigated the feasibility of cerium oxide (CeO₂) films as buffers layer of MFIS (metal ferroelectric insulator semiconductor) type capacitors. CeO₂ layer were prepared by a two-step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By applying a cerium (Ce) metal seed layer of 4 nm, unwanted SiO₂ layer generation was successfully suppressed at the interface between the buffer layer and the Si substrate. After N₂ plasma treatment, the leakage current was reduced by about 2-orders. By employing a N₂ plasma treatment, we were able to successfully obtain good properties at the interface between the buffer layer and the Si substrate.     

MOCVD of Pb(Zr x Ti1-x )O3 thin films on MgTiO3/Si substrates and their electrical properties

Abstract

Pb(Zh _x , Ti_1-x )O₃(PZT) thin films were deposited on Si substrates using MgTiO₃ as the buffer layer and the electrical properties of those MFIS structures were investigated. PZT and MgTiO₃ films were made by MOCVD using ultrasonic spraying technique. Perovskite PZT films have been succesfully made at the substrate temperature of 550 to 600°C only when using MgTiO₃ buffer layer. AES depth profile analysis and RBS analysis revealed that there is no remarkable interdiffusion and no formation of reaction layer between PZT and MgTiO₃ and/or between MgTiO₃ and Si substrate. The capacitance-voltage (C-V) curves of the MFIS structure which were made with PZT and MgTiO₃buffer layer have shown the hysteresis resulted from the ferroelectric switching of the PZT films.     

BaMgF4 thin film development and processing for ferroelectric FETS

Abstract

A ferroelectric memory field-effect transistor (FEMFET) where a ferroelectric thin film is incorporated directly into the gate structure of the transistor is attractive, because it provides not only nonvolatility, but also nondestructive readout (NDRO). At Westinghouse, we are currently developing a FEMFET using thin film barium magnesium fluoride (BaMgF₄), a ferroelectric material that was discovered in 1969, but was not fabricated in thin film form until 1989. The BaMgF₄ films are grown by evaporation in an ultrahigh vacuum (UHV) chamber on clean Si(100). The natural tendency of these films to grow with the ferroelectric a-axis in the Si(100) plane has been overcome to obtain more random orientation with larger reversible polarization perpendicular to the film. A capping layer (SiO₂) has been found to be essential for process integrability of these BaMgF₄ films. Ti-W metallization produced only a slight reduction in the capacitance-voltage (C-V) memory window. Switching speed of these films has been measured to be 40 to 45 nanoseconds. The first FEMFET fabricated with BaMgF₄ has exhibited 18 Volt memory hysteresis window with better than 10⁵ on/off current ratio for 20 Volt programming.     

The Effect of La-Doped Bi4Ti3O12 Buffer Layer on Crystallinity and Ferroelectric Properties of PbZr0.58Ti0.42O3/Bi3.25La0.75Ti3O12 Multilayered Thin Films

PbZr_0.58Ti_0.42O₃ (PZT) ferroelectric thin films with Bi_3.25La_0.75Ti₃O₁₂ (BLT) buffer layer of various thickness were fabricated on Pt/TiO₂/SiO₂/p-Si(100) substrates by rf-magnetron sputtering method. The pure PZT film showed (111) preferential orientation in the XRD patterns, and the PZT/BLT films showed (110) preferential orientation with increasing thickness of the BLT layer. There were no obvious diffraction peaks for the BLT buffer layer, for its thin thickness in PZT/BLT multilayered films. There were the maximum number of largest-size grains in PZT/BLT(30 nm) film among all the samples from the surface images of FESEM. The growth direction and grain size had significant effects on ferroelectric properties of the multilayered films. The fatigue characteristics suggested that 30-nm-thick BLT was just an effective buffer layer enough to alleviate the accumulation of oxygen vacancies near the PZT/BLT interface. The comparison of these results suggests that the buffer layer with an appropriate thickness can improve the ferroelectric properties of multilayered films greatly.     

Properties of PbZrxTi1−xO3/CeO2/SiO2/Si structure

Abstract

We report the crystalline quality and electrical properties of PbZr_xTi_1?xO₃ (PZT) films on n-type Si(100) substrates with CeO₂/SiO₂ dual buffer layers. PZT films and CeO₂ buffer layers were prepared by pulsed laser deposition technique, and SiO₂ buffer layers were formed by thermal dry oxidation. It was found that CeO₂/SiO₂ dual buffer layers effectively prevented Si and Pb interdiffusion between PZT and Si substrates. Furthermore, the capacitance-voltage (C-V) characteristics of the PZT/CeO₂/SiO₂/Si heterostructures demonstrated ferroelectric switching properties, showing a memory window as large as 2.7 V at 1 MHz.     

Reduction of Leakage Current by HfO 2 High K Dielectric Film Stacked on the Ferroelectric Layer of a MFIS Structure

We report here the reduction of leakage current through a thin ferroelectric layer by insertion of an HfO 2 film. We fabricated metal-insulator-ferroelectric-insulator-semiconductor (MIFIS) and metal-ferroelectric-insulator-metal (MFIS) structures. A Pb x La 1 m x TiO 3 (PLT) ferroelectric layer was deposited on a thermally oxidized p-type Si substrate with a Zr buffer layer. Adopting an HfO 2 layer on the ferroelectric layer of a MIFIS structure with an equivalent oxide thickness (EOT) of 5 nm resulted in a reduction by only 13 percent of the voltage distribution on the ferroelectric layer. Applying HfO 2 to the ferroelectric layer of a MFIS structure, however, led to a 70% decrease in leakage current: from 2.7 2 10 m 8 to 0.76 2 10 m 8 A/cm 2 at +1 V. An HfO 2 film, by itself, shows leakage that is 3 orders of magnitude smaller than that of PLT; clearly, insertion of the film impedes leakage through the ferroelectric layer. This characteristic is believed to contribute to extension of the retention time of MFMIS FETs.     

PREPARATION AND PROPERTIES OF LITHIUM-DOPED K0.5Na0.5NbO3 THIN FILMS BY CHEMICAL SOLUTION DEPOSITION

ABSTRACT

Lithium-doped K_0.5Na_0.5NbO₃ (KLNN) films were fabricated by chemical solution deposition on Pt/TiO₂/SiO₂/Si substrates. Homogeneous and stable precursor solutions were prepared by controlling the reaction of starting metal alkoxides. Perovskite KLNN single-phase thin films were successfully synthesized on Pt/TiO _x /SiO₂/Si substrates. The 0.75-μ m-thick KLNN film annealed at 650°C exhibited ferroelectric polarization hysteresis loops at ?250°C. The loop at room temperature was round, indicating the film contained leakage components. The dielectric constant under zero bias was 490 at room temperature. A typical upside-down butterfly DC bias-capacitance curve was obtained in the KLNN film capacitors at room temperature, indicating that polarization reversal occurred in the obtained KLNN films.     

MFIS and MFMIS structures using Pb(Zr,Ti)O3 films for nonvolatile memory devices

Abstract

In this work, metal / ferroelectric / insulator / semiconductor (MFIS) and metal / ferroelectric / metal / insulator / semiconductor (MFMIS) structures using Pb(Zr, Ti)O₃ (PZT) films were fabricated and characterized for nonvolatile NDRO memory device. 300nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO₄(ZT)/Si and Pt/ZT/Si substrates. C-V hysteresis were measured in both MFIS and MFMIS structures. By using a small-size MFM capacitor on a large-size MIS structure, it was found that the memory window of MFMIS structure was larger than that of the MFIS structure. There is a critical area ratio (S_MIS/S_MFM) in MFMIS structure. When an area ratio in MFMIS structure is below 12, the memory window increased with increasing area ratio. We could obtain that the memory window of MFMIS structure with a S_MIS/S_MFM of 11.8 was 2.1 V and 3.2 V with an applied voltage at 3 V and 5 V.     

Electrical characteristics of Pt-SBT-Polysilicon (MFIP) capacitors with yttrium oxide as the buffer layer

Abstract

MFIS structures with Strontium Bismuth Tantalate (SBT) as the ferroelectric thin film and yttrium oxide as the buffer layer have been fabricated on polysilicon layer as well single crystal silicon. Yttrium oxide film was deposited by electron beam evaporation and SBT was deposited by spin on MOD technique. Preliminary analysis of capacitance vs voltage (C-V) curve shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. For an applied DC bias of ± 5 V, the C-V curve shows a memory window of ± 2 V.     

Formation of Silicate-Added (Bi,La)4Ti3O12 Films on LaAlO3/Si(100) Structures

We fabricated MFIS (metal-ferroelectric-insulator-semiconductor) diodes with ((Bi,La)₄Ti₃O₁₂: BLT) films and lanthanum silicate (La₂SiO₅: LSO)-added BLT films formed on LaAlO₃/Si(100) structures. LaAlO₃ films were prepared by an MBD (molecular beam deposition) method. After the film deposition, they were subjected to ex site N₂ annealing in a rapid thermal annealing (RTA) furnace at 800°C for 1 min. BLT films and LSO-added BLT films were deposited on these LaAlO₃/Si structures using a sol-gel technique. The memory windows of BLT and LSO-added BLT films were 3.0 V and 2.1 V, respectively. It was found from the current density-voltage (I-V) characteristics that the insulation property of the LSO-added BLT film was superior to that of the BLT film. We conclude from these results that LaAlO₃ is an excellent candidate of a buffer layer for forming ferroelectric-gate FETs and that the LSO-added BLT film is suitable for low voltage operation of the FETs.     

PIMOD processing and properties of a LiNbO3-based MFSFET for nonvolatile memories

Abstract

The photo-induced metallo-organic decomposition (PIMOD) process has been successfully used to deposit a lithium niobate thin film acting as the gate oxide of the conventional MFSFET structure. The use of the low-temperature PIMOD process for thin film deposition has increased the device yields of the molybdenum liftoff for small area isolation. The electronic alteration of the properties of the ferroelectric gate transistor was previously shown to be caused by charges in the semiconductor being injected into the ferroelectric film. To prevent this problem, a thin SiO₂ buffer layer was thermally grown on the silicon substrate immediately before lithium niobate deposition. The silicon-lithium niobate interface was stabilized and the charge injection effect was eliminated due to the formation of the buffer layer. The channel current was shown to be greatly altered by the application of voltage pulses between the gate of the device and the substrate. Upon switching, the change in surface conductivity of the semiconductor was the same as that expected for ferroelectric switching.     

Improvement of the electrical properties of PZT thin films using TiO2 buffer layer

Abstract

Thin TiO₂ layers were sputter-deposited on Pt/Ti/SiO₂/Si wafers, as buffer layers for PZT thin film capacitors. It was found that TiO2 buffers of less than 4-nm-thickness could assist in obtaining highly uniform PZT thin films with no second phase. The leakage current behaviors of the PZT based capacitor are improved, while retaining the ferroelectric properties of PZT thin films such as remanent polarization and coercive field. In addition, the uniform distribution of oxygen in PZT on TiO₂/Pt indicates that the TiO₂ buffer layer act as a barrier for lead-platinum reaction, as well as for oxygen diffusion.     

Fabrication and Characterization of Ba(Ti,Zr)O3 Thin Films Through the Chemical Solution Deposition Process

Lead- and bismuth-free Ba(Ti_{1 ? x} Zr _x )O₃ (BTZ) thin films were fabricated on Pt(111)/Ti/SiO₂/Si(100) substrates by the chemical solution deposition (CSD) process. The single phase BTZ thin films were obtained at 650°C by conventional process and the control of lattice parameter a was possible by Zr substitution. As the D-E hysteresis loops and J-V characteristics depended on the precipitates on film surface, the fabrication process was reexamined by 2-step sintering process. Consequently the decreasing of first sintering time was able to prevent the precipitates, and the larger grain of about 40–50 nm were obtained by additional sintering for 2 hour.     

Thin film BaxSr1-xTiO3 ku- and k-band phase shifters grown on MgO substrates

Abstract

We report measurements of gold circuits fabricated on four Ba_xSr_1-xTiO₃ ferroelectric films doped with 1% Mn grown on MgO substrates by laser ablation. Low frequency (1 MHz) measurements of σ_T and tanδ on interdigital capacitors are compared with high frequency measurements of phase shift and insertion loss on coupled microstrip phase shifters patterned onto the same films. The variation in temperature of both high and low frequency device parameters is compared. Annealed with amorphous buffer layer and unannealed films are compared. Room temperature figures of merit of phase shift per insertion loss of up to 58.4°/dB at 18 GHz and 400 V dc bias were measured.     

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices

Abstract

We have investigated the roles of buffer layer in the Pt/SBT-Y₂O₃/p-Si (MFIS) capacitors. We found that the insertion of Y₂O₃ buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However, negative charges with the effective density of 3.21×10¹²/cm² were generated due to the additional process step for Y₂O₃ deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y₂O₃ buffer layer minimize the charge injection, the shift of the hysteresis loops was asymmetrical.     

Epitaxial structure SrBi2Ta2O9<116> /SrTiO3<011> /Ce0.12Zr0.88O2<001> /Si<001> for ferroelectric-gate FET memory

Abstract

Epitaxial thin film growth of SrBi₂Ta₂O₉/SrTiO₃/Ce_0.12Zr_0.88O₂ on Si was studied, and this epitaxial layer structure was applied to fabrication of ferroelectric-gate field effect transistors (FETs). The films were prepared by a pulsed laser deposition technique and epitaxial growth was identified by x-ray diffraction. The devices exhibited excellent electrical performances: Capacitance-voltage characteristic of a metal-ferroelectric-insulator-semiconductor (MFIS) diode showed a retention longer than 10 days and I_d-V_g characteristic of an MFIS-FET showed 1 day retention. It is proved that the crystalline quality of ferroelectric thin films is of great importance to develop integrated devices with high performance.     

Epitaxially grown ferroelectric thin film capacitors for sensing applications

Abstract

Pyroelectric infrared detectors based on La-modified PbTiO₃ (PLT) thin films have been fabricated by RF magnetron sputtering and micromachining technology. The detectors form PB_1?xLa_xTi_1?x/4O₃ (x = 0.05) thin film ferroelectric capacitors epitaxially grown in-situ by RF magnetron sputtering on Pt/ MgO(100) substrate. The sputtered PLT thin film exhibits highly c-axis oriented crystal structure (90%) that poling treatment for sensing applications is not required. The c-axis orientation ratio a of deposited PLT thin film strongly depends on the morphology of Pt layer, which in turn varies with the thickness of Pt layer on MgO substrate. We have successfully grown highly c-axis oriented PLT film on Pt electrode with a conductive percolating network structure. Micromachining technology is used to lower the thermal mass of the detector by coating Polyimide on top of the sensing elements to support the fragile structure and by selectively etching the backside of the MgO substrate to reduce the heat loss. The sensing element exhibited a low noise equivalent power (NEP) of 1.7 × 10^?10 W and a very high detectivity D? value of 8.5 × 10⁸ cmVHz/W at room temperature. The high performance for pyroelectric infrared sensing is primarily due to the highly c-axis oriented PLT thin film and its minimized thermal mass.     

CHARACTERISTICS OF METAL-FERROELECTRIC-INSULATOR-SILICON DEVICES USING HFSION BUFFER LAYERS

ABSTRACT

In this work, metal-ferroelectric-insulator-silicon (MFIS) devices were fabricated using HfSiON as buffer layers and their electrical properties were studied. Ultra-thin HfSiON films were fabricated by electron-beam evaporation at room temperature and post-annealed using different parameters such as temperature, time in O₂. By annealing a 2 nm-thick HfSiON film at 800°C for 60s in O₂, a negligible hysteresis loop and small equivalent oxide thickness of 2.3 nm were obtained with a corresponding leakage current density of 6.8 × 10^{? 5} A/cm² at a voltage shifted from the flat band voltage by 1 V. In the fabrication of MFIS diodes, Sr_0.8Bi_2.2Ta₂O₉ (SBT) films with 400 nm thickness were formed by chemical solution deposition. For Pt/SBT (400 nm)/HfSiON(2 nm)/Si diodes, a memory window of 0.8 V in width was observed during double capacitance-voltage sweep between +5 and –5 V. At the same time, excellent data retention properties were observed. The high and low capacitances in the hysteresis loop were well distinguishable even after 24 h had elapsed.