A Low Temperature LNO/PZT/LNO Ferroelectric Capacitor-Over-Interconnect (COI) FeRAM Module for Modular SOC

An embedded FeRAM module is achieved by a low temperature capacitor-over-interconnect (COI) process. A conductive perovskite LaNiO 3 (LNO) bottom electrode is used as seed layer; the crystallization temperature of in-situ sputter deposited PZT is greatly reduced to 350 C～400C. LNO's near-perfect lattice match with PZT allows PZT to grow epitaxially at low temperature. When LNO is used as top electrode of the ferroelectric capacitor, the fatigue performance is greatly improved. The COI LNO/PZT/LNO FeRAM structure achieved by this low temperature process is completely modular and is ideal for advanced Cu/low-K SOC (System On Chip) application. The COI FeRAM has been demonstrated successfuliy in a 64Kb(2T2C)-128Kb(1T/1C) dule-mode FeRAM with a 0.5 w m CMOS logic process.     

A 1.8 V 4 k FeRAM Chip Using 0.2 u Process and Novel Design Techniques

Due to the increasing demand for high speed, low voltage or low power applications, non-volatile memory becomes even more important and more challenging as technology advances. With ferroelectric memories, which provides fast write and fast read with relatively low power, the challenge is to provide a ferroelectric random access memory (FeRAM) chip that operates at low voltages with the smallest geometry available in the technology. In this paper, we present a 1.8 V 4 k bit ferroelectric memory chip design, with emphasis on core/core control, bit:cell determination and key circuit design as well as simulation results based on a 0.2 u CMOS double level metal process and ferroelectric process parameter assumptions.     

Circuits simulation of switch devices furnished with gain cell combined to FeRAM

Abstract

This paper has described a new concept on programmable switch device furnished with gain cell combined to FeRAM. Compared with memories but ferroelectric memories under many aspects, they have even been favorably labeled the ideal memory because of their non-volatility, ease of programming and operation by low voltage. As the programming switch, which is very attractive for logic application, SRAM, anti-fuse, flash type devices are well known. They have been required that satisfy non-volatility and low-voltage programming simultaneously. Some structures with ferroelectric material have been proposed and studied as solution of these problems. However, it seemed hard that these type devices are realized now from a viewpoint of fabrication process and low voltage operation. Therefore, we propose a new switch device furnished with gain cell combined to FeRAM. We have studied and simulated this switch device by SPICE. This basic circuit is composed of two blocks. One is switching block that includes gain cell, and the other is memory block that is FeRAM. Circuits, which we designed, amplify bit line's voltage up to Vdd or ground at sense amplification according to FeRAM data. The bit line voltage determines the logic state for gate electrode of switch transistor. The way to read is destructive read out. However, we can transfer information of bit line voltage during plate line is low-level voltage. The way to write FeRAM is similar to conventional way. It is revealed that the basic circuit with FeRAM connected gain cell could work correctly in simulation. In addition, this kind of device is hopeful of many logic applications.     

First 0.18 μm SBT-Based Embedded FeRAM Technology with Hydrogen Damage Free Stacked Cell Structure

An SBT-based embedded FeRAM has been successfully developed for the first time, which has been fabricated by using the 0.18 μm CMOS multi-level metal logic process. The highly-reliable FeRAM characteristics have been attained by the newly developed stacked cell structure which is fully enveloped by the top and bottom hydrogen barriers, resulting in the elimination of the hydrogen damage of the 0.18 μm multilevel metal process. The developed 0.18 μm SBT-based embedded FeRAM technology is most promising for commercialization of 0.18 μm embedded FeRAM and beyond.     

Signal Window Map--A New Analysis Tool for FeRAM

The properties of a ferroelectric capacitor are usually described by a hysteresis curve. However for high density FeRAM there is hardly any chance to measure the hysteresis curves for all cells directly. The only information that can be obtained by testing FeRAMs is of a digital nature: a cell is passing or failing. In order to quantify the quality of each cell capacitor individually, a new signal window analysis method has been developed. During a READ access in FeRAM operating in ITIC mode the stored signal of a memory cell is usually coupled to a bitline and then compared to a reference (Takashima et al. [1]). In ordr to optimize the reference voltage signal distributions for 0 (non switching) and 1 (switching) data have to be measured for the whole memory array. The voltage difference between the 0 and 1 signal of each individual cell determines this cell's signal window. This signal window describes the quality of a memory cell and it is analog information about the memory cell's performance. Plotting each cell's signal window value in a bit map using different colors for different signal windows gives a very sensitive tool for the analysis of the spatial distribution of the signal window. Since cell signals are directly related to their hysteresis properties the signal window map also gives information about the hyteresis variations across the chip. In addition, circuit properties that affect signal as well as process influences can be seen easily in this picture. Using the signal window map for the analysis of signal affecting parameters like write-voltage or timing proved to be a very sensitive tool to distinguish the influence of these parameters. In sum this analysis method provides feedback for process and technology development as well as for circuit analysis.     

Integration of H2 barriers for ferroelectric memories based on SrBi2Ta2O9 (SBT)

Abstract

In this study, integration of an hydrogen barrier into a FeRAM process flow is investigated. It is reported in the literature that ferroelectric properties can be maintained after hydrogen annealing by using IrO_x as a top electrode [16][17][18]. Advantage of materials like IrO_x is less catalytic activity compared to Pt. However, we found that IrO_x is not a promising candidate for top electrode barrier. (Pt)/IrO_x/SBT/Pt capacitors are prone to shorting or exhibit high leakage. IrO_x films are very easily reduced by reducing ambient which will result in peeling off. Also, IrO_x films tend to oxidize Ti or TiN layers immediately. Therefore, other barrier materials or layer sequences like Ir/IrO_x have to be considered.

For protection of the entire capacitor an Encapsulation Barrier Layer (EBL) is required. In this study, LPCVD SiN is used. LPCVD SiN is a standard material in CMOS technology. Production tools are available and it is well known as hydrogen barrier. By modifying the deposition process and using a novel process sequence, no visual damage of the capacitors after SiN-deposition and FGA is seen. Also, no degradation of electrical properties after capacitor formation as well as after SiN-deposition and FGA is observed. However, after metal 1 and metal 2 processing, 2P_r values at 1.8V are reduced from 12μC/cm²to 2μC/cm². Polarization at 5.0V is not affected.     

An improved behavioral model of ferroelectric capacitors

Abstract

An improved behavioral model for ferroelectric capacitors is proposed successfully. This model gives accurate simulation results for FeRAM writing and reading process, which helps to the optimization of FeRAM circuit design. The model can also be adapted to express the P-V characteristic of a FE capacitor imposed by nonsymmetrical voltage.     

Process Integration of Embedded FeRAMs

This paper describes the general aspects of embedding Ferroelectric Memories (FeRAMs) with logic circuits and/or microcontrollers. These devices and stand-alone memories constitute the main thrust of applications of ferroelectric memories. The problems associated with embedding test the robustness and compatibility of the FeRAM process with established CMOS integrated circuits. As integrated circuits technology advances in lithography, FeRAMs meet the challenge, but new problems appear. In this review, existing embedded FeRAMs of the 0.8/0.6 generation will be discussed. A program for the 0.35/0.25 generation, and the 0.18 challenges are outlined and addressed. The paper also reviews the application of FeRAM Smart Cards. This application is becoming the best example of embedded FeRAMs in which to demonstrate the System-One-Chip technology direction. Smart Card ICs clearly take advantage of the low power, high-write speed and long endurance characteristics of Ferroelectric Memories.     

Polarization Switching DC-to-DC Converters

Abstract – On-chip DC-to-DC converters are critical to ensure regulated voltage for a variety of DC applications, including automotive and personal computer products. The converters have historically been limited to low power applications due to the size and cost constraints involved with the desire to have the converters integrated with the application circuit. The latest technology involves using switched-capacitors to allow for lower cost and monolithic integration. A new DC-to-DC converter design, utilizing a ferroelectric (FE) capacitor is researched, fabricated and tested. The inclusion of a FE, switched-capacitor results in an increase in the converter's output voltage due to the high dielectric constant (high-k) of the capacitor in conjunction with the resulting switching current as the polarization of the capacitor is reversed. In fact, the FE capacitor's effective capacitance resulting from the polarization switching provides the same behavior as a linear capacitor that is approximately 10 times the size (with respect to capacitance) as the FE capacitor. A proposed ferroelectric-based DC-to-DC step-down converter is analyzed, simulated, fabricated and tested. The results show the FE capacitor-based converter provides an output voltage and output impedance advantage over linear capacitor-based converters for equivalent capacitance levels.     

The reliability of FeRAMS with 2T/2C or 1T/1C type cell structure

Abstract

Ferroelectric Random Access Memory (FeRAM) provides some advantages such as non-volatility, high endurance on write/read cycles, high radiation hardness and low power consumption compared to conventional memories. However, in order to realize a commercial FeRAM, it is important to overcome the limitation in various reliability items such as retention, imprint, and fatigue failure at high operation temperature. In this paper, the retention characteristic of FeRAM related with imprint degradation of ferroelectric capacitors at high temperature is evaluated on the level of 8” wafer. Both cell configurations of 2T/2C and 1T/1C are discussed in terms of imprint reliability. General reliability items of the FeRAM after TSOP-I type package, such as fatigue endurance, early failure rate (EFR), humidity acceleration stress test (HAST), and temperature cycle (TC), are also evaluated.     

Platinum (100) Hillock Growth in Pt/Ti Electrode Stack for SrBi2Ta2O9 Ferroelectric Random Access Memory

The ferroelectric material SrBi₂Ta₂O₉ (SBT) has been extensively investigated in connection with integrating nonvolatile ferroelectric random-access memory (FeRAM). The SBT layer must be annealed in an oxygen atmosphere after deposition to crystallize the ferroelectric oxide film, which induces Pt hillock formation in a Pt/Ti electrode stack. The Pt hillock in a Pt/Ti electrode stack has been the main concern in SBT FeRAM due to reliability problems, such as capacitor shorts. Reportedly, the compressive stress generated in thin film is widely accepted as being responsible for the occurrence of hillocks in thin film and the main mass transport mechanism for hillock formation is the grain boundary diffusion for thin film with a columnar structure. In this study, three factors are considered in the total compressive stress generated during both deposition and post-annealing in Pt/Ti electrode stack: intrinsic stress, thermal stress, and extrinsic stress. Moreover, we found that an orientation relationship of Pt (100)_hillock//Pt (111)_{thin film} existed between the Pt hillock and the thin film. The Pt hillock was a single crystal, having facets with polyatomic steps. From these results, we suggest that the Pt hillock growth mechanism is the layer growth of flat faces, which shapes the hillock into a tetrahedron single crystal.     

Plasma Etch Processes for Embedded FRAM Integration

We describe the etch processes used for integration of embedded ferroelectric random access memory (FRAM) within a standard CMOS logic flow. The ferroelectric module is inserted following front-end contact formation and prior to backend integration using only two additional mask levels: capacitor pattern and bi-level via pattern. The single-mask stack etch process employs a TiAlN hardmask to define Ir/IrO_x/PZT/IrO_x/Ir capacitors. Protective sidewalls can be formed using an etchback process. The bi-level via etch and subsequent metal fill processes complete the FRAM module formation. Functional 4 MB arrays embedded with 5 levels of Cu/FSG integration have been demonstrated.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

燃料电池用碳材料的研究进展

碳材料因其具有独特的物化性能以及各异的形态而成为电池部件的重要原材料,广泛应用于燃料电池中。以质子交换膜燃料电池(PEMFC)为例,介绍了燃料电池中电极基质、双极板、担体碳和贮氢碳材料的研究进展。涉及燃料电池电极基质和双极板的制备工艺与性能,以及催化剂担体碳的不同粒度、聚集形态对催化剂活性的影响。并对纳米碳贮氢材料在燃料电池方面的研究应用做了简单的评述。     

A low jitter sub-sampling phase-locked loop with sampling thermal noise cancellation technique

The traditional sub-sampling phase-locked loop faces the tradeoffs between phase noise and spur, in that low in-band phase noise requires large sampling capacitor size but at the sacrifice of spur performance. This paper presents a sub-sampling PLL aimed at minimizing in-band phase noise via sampling thermal noise cancellation technique. It enables the substantial reduction of in-band phase noise while reducing the sampling capacitor size. In addition, due to the reduction of the sampling capacitance, the reference spur performance of the PLL is improved, and the power consumption of the isolation buffer is reduced. Implemented in a 65 nm CMOS process, the in-band phase noise at 200 kHz offset is −133.4 dBc/Hz at 2.2 GHz and integrated jitter is 80 fs_rms. The reference spur is −67 dBc. It consumes 5.5 mA from 1.2 V supply and occupies 0.72 mm².     

High density and long retention non-destructive readout FeRAM using a linked cell architecture

Abstract

A 64 Kbit non-destructive readout (NDRO) ferroelectric random access memory (FeRAM) using a 0.6-μm technology is described. The NDRO FeRAM uses a novel linked cell architecture, which minimizes the circuit overhead accepted in Flash memories. This test device has shown 10-year retention and unlimited read operation. An 120-ns NDRO operation is performed at a read voltage of 2.2V. Circuit techniques used in the NDRO FeRAM include: (1) direct programming of ferroelectric capacitors, (2) automatic restoring of read data, and (3) data storing under zero bias conditions. The unique linked cell architecture allows for scaling a cell size down to 6F ², where F is the minimum feature size available.     

Important Considerations for Capacitor Applications in the Petroleum and Chemical Process Industries

An overview of capacitor applications is presented, with emphasis on the petroleum and chemical process industries, highlighting factors proven to be important. Subjects such as capacitor bank size and location, design, harmonics, switching, reclosing, and protection are considered. Guidelines are given to assist with the proper selection and design of the capacitor installation, with some examples to illustrate techniques for analysis.     

六英寸Si基GaN功率电子材料及器件的制备与研究

氮化镓(GaN)作为第三代半导体材料的代表,具有优异的材料物理特性,更加适合于下一代电力电子系统对功率开关器件更大功率、更高频率、更小体积和更恶劣工作温度的要求。为了兼容Si基CMOS工艺流程,以及考虑到大尺寸、低成本等优势,在Si衬底上进行GaN材料的异质外延及器件制备已经成为业界主要技术路线。详细介绍了在6英寸Si衬底上外延生长的AlGaN/GaN HEMT结构功率电子材料,以及基于6英寸CMOS产线制造Si基GaN功率MIS-HEMT和常关型Cascode GaN器件的相关成果。     

柔性直流输电功率模块电容的在线监测

对于柔性直流工程所用的薄膜电容来说,其容量的衰减程度是电容老化和健康状态的重要指标。在回顾典型的电容容量估算方法的前提上,针对模块化多电平拓扑的柔性直流换流阀分析了实际工程中的测量数据所遇到的两种主要误差:采样噪声和同步误差。在此基础上,考虑了最近电平调制的特点,计算了功率模块在每个切除状态下的电容电压平均值和每个投入状态下的桥臂电流积分,利用最小二乘法设计了在线电容容量估算的方案。与其他两种方案的仿真对比表明,所提方法对采样噪声和同步误差敏感度低,算法简单计算量小,适用于实际工程。     

Multilevel converters-a new breed of power converters

Multilevel voltage source converters are emerging as a new breed of power converter options for high-power applications. The multilevel voltage source converters typically synthesize the staircase voltage wave from several levels of DC capacitor voltages. One of the major limitations of the multilevel converters is the voltage unbalance between different levels. The techniques to balance the voltage between different levels normally involve voltage clamping or capacitor charge control. There are several ways of implementing voltage balance in multilevel converters. Without considering the traditional magnetic coupled converters, this paper presents three recently developed multilevel voltage source converters: (1) diode-clamp, (2) flying-capacitors, and (3) cascaded-inverters with separate DC sources. The operating principle, features, constraints, and potential applications of these converters are discussed