Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board

A new design on the electrostatic discharge (ESD) protection scheme for CMOS IC operating in power-down-mode condition is proposed. By adding a VDD_ESD bus line and diodes, the new proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line to avoid malfunction during power-down-mode operating condition. During normal circuit operating condition, the new proposed ESD protection schemes have no leakage path to interfere with the normal circuit functions. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both VDD power line and VDD ESD bus line. Experimental results have verified that the human-body-model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-μm silicided CMOS process. Furthermore, output-swing improvement circuit is proposed to achieve the full swing of output voltage level during normal circuit operating condition.     

Design on ESD protection scheme for IC with power-down-mode operation

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-/spl mu/m silicided CMOS process.     

On-chip ESD protection design by using polysilicon diodes in CMOSprocess

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC     

Improved ESD properties by combining GaN-based light-emitting diode with MOS capacitor

An InGaN/GaN light-emitting diode (LED) combined with a metal–oxide semiconductor (MOS) capacitor has been fabricated for high electrostatic discharge (ESD) protection. By connecting a MOS capacitor in parallel with the GaN-based LED, a level of defense against the ESD is significantly strengthened from 200 to 1900 V of human body mode (HBM), which corresponds to 6- to 7-fold enhancement in the ESD robustness of LEDs.     

Design optimization of ESD protection and latchup prevention for a serial I/O IC

ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC’s during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness.     

SiGe工艺中HBT结构ESD保护电路设计

为有效控制生产成本,减少工艺步骤,提出了在SiGe工艺中,用SiGe异质结双极型晶体管(HBT)代替传统二极管来实现静电放电(ESD)保护的方案。通过设计不同的HBT器件的版图结构,以及采取不同的端口连接方式,对HBT单体结构防护ESD的能力强弱和其寄生电容大小之间的关系进行了比较分析,并从中找出最优化的ESD解决方案。应用于实际电路中的验证结果表明,此方案在ESD防护能力达到人体模型(HBM)2 kV的基础上,I/O(IN/OUT输入输出)端口的寄生电容值可以做到200 fF以下,且此电容值还可通过HBT串联模式进一步降低。     

双向可控硅器件在片上静电防护中的应用

设计了一种用于芯片静电放电(ESD)防护的双向可控硅(DDSCR)器件.该器件具有对称性或非对称性骤回I-V特性,可以用于多种应用场合.器件的最优静电防护性能达到94 V/μm.简洁的器件结构用于输入/输出保护,对内部电路的寄生效应小,人体模型ESD测试达到耐压等级3(超过4 kV).在多电源芯片的静电防护中,双向可控硅器件可克服普通器件不能胜任的多模式静电事件的发生.首次提出了双向可控硅器件在高速多媒体接口中静电防护和反向驱动保护的应用.     

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

This paper reports an ESD internal gate-oxide damage occurred on the digital-analog interface of a mixed-mode CMOS IC. A new ESD protection method is proposed to rescue this internal gate-oxide damage by adding ESD-protection devices on the long metal line between digital-analog interfaces. Experimental verification has confirmed that the IC product can be rescued to pass 2-KV ESD stress from the digital/analog VDD to digital/analog VSS pads without causing any internal damage again.     

一种系统级封装的ESD保护技术

介绍了一种系统级封装(SiP)的ESD保护技术。采用瞬态抑制二极管(TVS)构建合理的ESD电流泄放路径,实现了一种SiP的ESD保护电路。将片上核心芯片的抗ESD能力从HBM 2 000 V提升到8 000 V。SiP ESD保护技术相比片上ESD保护技术,抗ESD能力提升效果显著,缩短了开发周期。该技术兼容原芯片封装尺寸,可广泛应用于SiP类产品开发中。     

Wide range control of the sustaining voltage of electrostatic discharge protection elements realized in a smart power technology

Highly efficient electrostatic discharge (ESD) protection structures with a sustaining voltage >40 V are realized in a smart power technology. They guarantee an excellent ESD protection at high voltage pins without the danger of transient latch-up. Compared to the vertical npn transistor a shift of the sustaining voltage of 21 V has been achieved purely by a layout modification of the buried layer. The high ESD performance has been proven on product level by an ESD hardness of >8 kV (HBM).     

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-/spl mu/m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 /spl plusmn/ 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 /spl plusmn/ 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.     

ESD protection design on analog pin with very low input capacitancefor high-frequency or current-mode applications

An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~1.0 pF (including the bond-pad capacitance) for high-frequency applications     

Stacked-NMOS triggered silicon-controlled rectifier for ESDprotection in high/low-voltage-tolerant I/O interface

A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using a thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35 μm CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 μm can be obviously improved from the original ~2 kV to be greater than 8 kV by this SNTSCR device with device dimensions of only 60 μm/0.35 μm     

IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

亚微米CMOS工艺中GG-NMOS结构ESD保护电路改进设计

针对采用GG-NMOS结构ESD保护电路的IC芯片在实际应用中出现ESD失效现象,在不额外增加版图面积的情况下通过引入栅耦合技术对现有的ESD保护结构进行改进,并达到了预期效果.实验结果显示其性能达到了人体放电模式的2级标准(HBM:3000V),机器模式3级标准(MM:400V).     

抗辐照SOI256kB只读存储器的ESD设计

ESD设计技术已成为业界提升SOI电路可靠性的一个瓶颈技术。文章介绍了一款具有抗辐照能力、基于SOI／CMOS工艺技术研制的容量为256kB只读存储器电路的ESD设计方案。结合电路特点详细分析了其ESD设计的难点,阐述了从工艺、器件和电路三个方面如何密切配合,进行SOI电路ESD设计的分析思路和解决方法。电路基于0．8...     

Design of fabrication of ESD protection circuit with high holding voltage for power IC

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.     

Cancellation technique to provide ESD protection for multi-GHz RF inputs

A technique to provide ESD protection for multi-GHz R-F inputs is presented. It provides protection against both human body model (HBM) and charged device model (CDM) type events with minimal effect on RE performance. A 5.25 GHz LNA protected by this means has a measured HBM ESD protection level of 3.6 kV.     

Designing power supply clamps for electrostatic discharge protection of integrated circuits

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.