A methodology for microcontroller signal frequency stress prediction

This paper proposes a methodology for analysis and prediction of microcontroller failures due to signal frequency stress. Microcontrollers are constantly under signal frequency stress when controlling external devices. However, signal frequency stress has received relatively little attention in comparison with other sources of stress such as temperature, humidity, and voltage. This study involved the following steps: (1) identifying the highest stress point before failure; (2) dividing signal frequency into different stress levels; (3) characterizing the impact of signal frequency stress on IC functionality; (4) constructing a thermal profile of a microcontroller under signal frequency stress over time; (5) predicting stress levels using regression and neural network methods; and (6) comparing and contrasting performance differences for each method. Results indicated that the average prediction error is about 7.9% for the neural network approach and about 23.8% for the statistical regression approach. This may be due to the neural network modeling approach’s inherent ability to tolerate noise in the data due to factors such as variation in quality due to variations in the manufacturing process. This general methodology has also been utilized with low error rates in failure analysis and stress prediction in operational/power amplifiers (8% error rate), timer oscillator chips (25%) and resistors (30%).     

CMOS LC VCO中交叉耦合MOS管的结构和特点

在近年来的文献报道中,CMOS LC VCO中交叉耦合MOS管的电路结构变化多端.在不同的设计中,MOS管的类型、数目和连接方式有很多不同的结构.从其基本结构出发总结这些结构,就不同结构MOS管电路对振荡器性能做了简要分析.着重介绍了近年来在理论认识,低电压、低相位噪声和宽频率覆盖设计方面所做的努力.     

Optimal simple step-stress plan for Khamis-Higgins model

Optimal times of changing stress-level for the simple step-stress plans under the Khamis-Higgins model (an alternative to the Weibull step-stress model) are determined for a wide range of values of the model parameters. The applicability of the "optimal time of changing stress" formula obtained by Khamis-Higgins for a known shape parameter to the case of unknown shape parameter is examined. Their formula provides a reasonable approximation to the actual optimal times of changing stress levels within a certain range of values of the stress levels and model parameters but a poor approximation outside of that range     

高电源抑制比低噪声带隙基准电压源的设计

基于带隙基准原理,通过优化电路结构和采用BiCMOS技术,提出一种精度高、噪声小的带隙基准源电路。利用具有高开环增益的折叠式共源共栅放大器,提高了低频电压抑制比;应用低跨导PMOS对管及电路输出端低通滤波器,实现了更低的噪声输出;合理的版图设计减小了失调电压带来的影响。Hspice仿真结果表明,在3V电源电压下,输出基准电压为1.2182mV,温度系数为1.257×10-5/℃;频率从103～105 Hz变化时,输出噪声最大值的变化量小于5μV。流片测试结果表明,该基准源输出基准电压的电源抑制比高,温度系数小,噪声与功耗低。     

New basic unit and cascaded multilevel inverters with reduced power electronic devices

ABSTRACT

In this paper, a new cascade multilevel inverter based on series connection of several basic units is proposed. The basic topology consists of 5 dc voltage sources and 12 switches. The required mathematical analysis consisting of voltage on switches, power losses and the values of dc voltage sources is provided. To verify the advantages of proposed topology, the suggested structure is compared with other multilevel inverter topologies in terms of used dc voltage sources, switches, voltage on switches and the number of on-state switches. The proposed structure uses the least numbers of dc voltage sources and switches compared to other multilevel inverters for the same number of levels. Also, voltage rating on the switches in the proposed topology is less than other topologies. These characteristics cause the weight, size and cost of proposed topology to be reduced. The proposed inverter is implemented using experimental setup. The experimental results verify the performance of proposed structure.     

Helpful hints to select a power-factor-correction solution for low- and medium-power single-phase power supplies

This work presents a review of power-factor-correction (PFC) circuits for low- and medium-power single-phase power supplies. The main idea is not just to show the state of the art of this topic but to select the most interesting topologies for each application depending on the power level, the input voltage range, and the output voltage. Since IEC 61000-3-2 regulations came into force, many new topologies have been presented trying to obtain a cost-effective solution to reduce the input current harmonic content. Each one of them has its application range due to the inherent characteristics of the topology. Obviously, not every converter is useful for the same application. This is especially perceptible in PFC circuits due to the large amount of different solutions. Hence, this paper tries to show the most appropriate topologies for each application, being the input power and the IEC 61000-3-2 Class some of the main parameters to select it. The scope of the paper is focused on single-phase power supplies belonging to IEC 61000-3-2 Class A and Class D with an input power level below 4 kW.     

单级功率因数校正电路及其开关应力分析

文章给出了几种单级功率因数校正电路的拓扑结构，计算和分析了其功率开关管上的电压应力和电流应力。为设计功率因数校正电路选择适宜的电路拓扑结构提供了一种依据。     

Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13 µm CMOS

Portable and implantable device applications require low supply voltage reference circuits due to increasing trend for lower power requirements. Voltage references have been proposed for operation below 1 V for CMOS and a comprehensive analysis of the behavior of the different topologies is needed for ultra-low power designs, in order to select the right circuit topology for a given requirement. This work compares two major classes of voltage reference topologies: threshold voltage (V_T0)-based and (V_G0) bandgap voltage-based reference circuits. Four different topologies of voltage-reference designs with 1-V supply were designed and fabricated in 130 nm CMOS process. Monte Carlo analysis shows the variability of the references and of their temperature coefficients (TC), and the results are compared to measured samples. Simulations and measurements show that the threshold voltage-based references are more susceptible to the variations in the CMOS fabrication process.     

A zero voltage transition boost converter employing a soft switching auxiliary circuit with reduced conduction losses

This paper presents a zero-voltage-transition (ZVT) boost converter using a soft switching auxiliary circuit for power factor correction (PFC) applications. The improvement over existing topologies lies in the positioning of the auxiliary circuit capacitors and the subsequent reduction in the resonant current and therefore the conduction losses as compared to other similar topologies. The proposed converter operates in two modes - Mode 1 and Mode 2. It is shown in the paper that the converter should be designed using the constraints obtained in Mode 1 to achieve low-loss switching. The converter is analyzed and characteristic curves presented which are then used in a detailed design example. Experimental results from a 250 W, 127 V input laboratory prototype switching at 100 kHz verify the design process and highlight the advantages of the proposed topology. The proposed converter is suitable for single-phase, two stage power factor correction circuits with universal input voltage range and power levels up to 3 kW.     

Novel half-bridge resonant converter topology realized by adjustingtransformer parameters

This paper shows a new direction as to how the transformer parameters may be best utilized and presents the performance and control of novel DC/DC and AC/DC converter topologies. All three inductances of a transformer have been utilized to realize a CL³ topology having excellent characteristics and requiring no external inductor. For the half-bridge topology, the capacitor used for the purpose of input voltage splitting also serves as the resonating capacitor. Thus, in the half-bridge version, the topology is realized only with a specially designed transformer and no other external components. A laboratory setup is produced and experiments conducted for DC/DC and AC/DC applications. A new design procedure and control technique for the converters are also presented. These topologies are very promising in small-power applications     

Utilization of an active-clamp circuit to achieve soft switching inflyback converters

Flyback derived power convertor topologies are attractive because of their relative simplicity when compared with other topologies used in low power applications. Incorporation of active-clamp circuitry into the flyback topology serves to recycle transformer leakage energy while minimizing switch voltage stress. The addition of the active-clamp circuit also provides a mechanism for achieving zero-voltage-switching (ZVS) of both the primary and auxiliary switches. ZVS also limits the turn-off di/dt of the output rectifier, reducing rectifier switching losses, and switching noise due to diode reverse recovery. This paper analyzes the behavior of the ZVS active-clamp flyback operating with unidirectional magnetizing current and presents design equations based on this analysis. Experimental results are then given for a 500 W prototype circuit illustrating the soft-switching characteristics and improved efficiency of the power converter. Results from the application of the active-clamp circuit as a low-loss turn-off snubber for IGBT switches is also presented     

Multiband High-Linearity Front-end Receivers for Wireless Applications

In this paper, a modified front-end receiver configuration, which consists of an LNA and mixer suitable for zero-IF or low-IF receivers, is presented. The idea is to achieve a better linearity for receivers by combining circuit and system level solutions. Three circuit topologies, two in bipolar and one in CMOS technology, are presented in this paper with their simulation results. One of the bipolar topologies has been implemented and measurement results are presented. An IIP₃ of up to +0.6 dBm of a combined bipolar LNA and mixer is achieved, depending on frequency of interest and with an acceptable noise figure performance at a current consumption of less than 13 mA from 5 V supply voltage in one circuit and 3 V supply voltage in the other one. An IIP₃ up to +5 dBm is achieved for the CMOS topology at a lower overall gain and acceptable noise figure (14.4 mA and 3 V). All circuits presented in this paper are wideband circuits, suitable for area-efficient multiband receivers.     

Resonant converter topologies with three and four energy storageelements

Generalized half-bridge and full-bridge resonant converter topologies with two, three and four energy storage elements are presented. All possible circuit topologies for such converters under voltage/current driven and voltage/current sinks are discussed. Many of these topologies have not been investigated in open literature. Based on their circuit element connections and source and load excitation types, these topologies are classified into resonant and nonresonant topologies and on their physical realizability. Comparison based on exact steady state analysis are given for typical second- and third-order series resonant converters whereas the fourth-order topology is based on the approximate analysis     

一种改进的二极管箝位型多电平变换器拓扑

多电平电路在高压大功率领域的拓展受到其复杂电路拓扑的制约,因此近年来不断有新型多电平电路结构被提出。本文在传统多电平逆变器拓扑结构的基础上,提出了一种新型单相七电平电压源逆变器拓扑。新型电路拓扑是在传统的单相全桥五电平箝位二极管电路基础上,增加了两个开关器件,利用10个开关器件以及4个箝位二极管产生了7种不同的电平输出。详细分析了该逆变器的拓扑结构,给出了PWM控制策略。最后通过仿真实验验证了这种拓扑的可行性。该逆变器对传统箝位二极管逆变器在结构上做出了优化。     

Analysis and design of a practical discontinuous-conduction-modeBIFRED converter

Impending international standards on harmonic current levels drawn by single-phase mains-operated equipment have created a need for low-cost off-line power-factor-corrected switched-mode power supply topologies in the power range up to a few hundred watts. The boost integrated/flyback rectifier/energy storage/DC-DC converter (BIFRED) is one such topology which shows promise in this regard. In particular, the discontinuous-conduction-mode (DCM) BIFRED avoids the light-load high-voltage stress problem associated with the continuous-conduction-mode design, while still achieving the combined advantages of a low-cost single-stage topology with high displacement factor and low total harmonic distortion. In this paper, a practical DCM BIFRED converter with integrated low-loss snubber is investigated from both power and small-signal control perspectives. Design equations are given to ensure DCM operation under closed-loop output voltage control, in which switch duty cycle is varying. Experimental results on a prototype converter are also presented     

Monolithic feedback low noise X-band amplifiers using 0.5-μmGaAs MESFETs: comparative theoretical study and experimentalcharacterization

Three different feedback low-noise-amplifier (LNA) circuit topologies for simultaneous noise and power matching are theoretically investigated and compared for the X-band application. The smallest minimum noise figure (NF_min) is shown to be achieved by the common source parallel feedback (CSPF) topology, while the common source series feedback (CSSF) topology exhibits the best overall performance. Experimentally, a CSSF three-stage LNA has been fabricated using 0.5-μm-gate GaAs MESFETs and systematically characterized. In this LNA circuit, an optimal series feedback for noise figure, gain, and stability is implemented via a proper choice of the short stub length. The size of the fabricated monolithic microwave integrated LNA chip is only 1 mm²/stage. The measured gain varies from 22.0 to 23.0 dB in the frequency range of 8 to 10 GHz, with good flatness. The input/output voltage standing wave ratios are less than 2 and 1.43, respectively. The noise figure of the three-stage LNA is less than 2.6 dB. These measured data are sufficient for practical applications and are also in good agreement with simulated results     

高精度低噪声基准电压源的设计

利用反向带隙电压原理,采用基于CMOS阈值电压的自偏置共源共栅电流镜技术,设计了一种低压低噪声基准电压源.该电压基准源没有外加滤波电容的情况下,通过双极型晶体管大的输出阻抗特性,实现了更低的噪声输出,提高了输出电压的精度.Hspice仿真结果表明,在0.95V电源电压下,输出基准电压为233.9 mV,温度系数为7.6...     

Reduction in controlled power switches for a single-phase novel multilevel inverter

Multilevel inverter (MLI) generates stepped voltage with appropriate switching combination of power devices, thus restraining the requirement of filter circuit for an efficient power conversion. MLIs are attracting due to some of the major features like economic cost, installation space, bulkiness, complexity along with its enormous applications in industries like cement factory, ceramic industry, aerospace applications etc. In this paper, a single-phase generalised inverter based on five different algorithms is proposed that uses the minimum of overall power components. The presented topology can be used in low and medium voltage applications. To verify the simulation results obtained by MATLAB/Simulink, DS1103 controller is used to generate the corresponding experimental results by developing a prototype model in the laboratory. Nevertheless, a comparative assessment for the different required components of the proposed topology is carried out with some recently developed topologies. Reduction in power switches, driver circuits and DC voltage sources reduces the size, cost, complexity and enhances the overall performance. In addition, level per switch ratio is added in this paper to decide the effectiveness of the proposed topology.     

Accelerated life-tests for intermittent destructive inspection,with logistic failure-distribution

Statistically-optimal accelerated life-test plans are suggested for items whose lifetime follows a logistic distribution. Both the scale and location parameters of the lifetime distribution are functions of the stress level. The test plans accommodate intermittent destructive sampling. The number of sampled items which fail to pass the test at the time of each inspection follows a hypergeometric distribution; the number of defective items in the remaining sample which have not yet been tested follows a binomial distribution. Statistically-optimal designs provide test planners with a set of design inputs, such as: 2 stress-levels higher than use stress-level, a set of inspection times, sample allocation, and a censoring time that minimizes the asymptotic variance of the maximum likelihood estimator of a specified quantile of the lifetime distribution. However such a 2 stress-level optimal plan is not practical because model validation is rarely impossible with so few stress-levels at which to test. In order to overcome such impracticality compromise plans that require 3 stress-levels are also suggested at a fixed inspection interval-although these plans lose statistical efficiency     

半导体温度传感器在远程测量和变送中的应用

根据工业现场的实际应用需要,结合Maxim半导体温度传感器系列产品的特点,提出了多种适合于远程温度测量的应用结构,具有极高的实际应用价值,并且首次提出了创新的三维立体测量结构和基于电流环的电压调制和电流调制的信号传输技术。