考虑信号相关性的逻辑电路可靠度计算方法

随着集成电路特征尺寸不断缩小,软错误已经成为影响电路可靠性的关键因素.计算软错误影响下逻辑电路的信号概率能辅助评估电路的可靠性.引起逻辑电路信号概率计算复杂性的原因是电路中的扇出重汇聚结构,本文提出一种计算软错误影响下逻辑电路可靠度的方法,使用概率公式和多项式运算,对引发相关性问题的扇出源节点变量作降阶处理,再利用计算得到的输出信号概率评估电路可靠度.用LGSynth91基准电路、74系列电路和ISCAS85基准电路为对象进行实验,结果表明所提方法准确有效.     

基于一种交织码的多位翻转容错技术研究

随着技术的发展和核心电压的降低,存储器更易受瞬时错误（软错误）影响,成为影响航天器件可靠性的主要原因。错误检测与纠正（EDAC）码（也称错误纠正码）常用来对SRAM型存储器中的瞬时错误进行纠正,由单个高能粒子引起的多位翻转错误（SEMU）是普通纠一检二（SEC-DED）编码所无法处理的。提出了一种交织度为2的(26,16)交织码,该码由两个能纠正一位随机错误、二位突发错误的(13,8)系统码组成,(26,16)交织码能够纠正单个码字中小于二位的随机错误和小于四位突发错误（DEC-QAEC）。通过理论分析和硬件平台实验表明,该交织码在存储资源占用率、实时性相当情况下可靠性优于同等长度的SEC DED码,能有效提高SRAM型存储器抗多位翻转错误的能力。      

可逆电路中门失效错误的定位方法

可逆电路是量子计算科学,低能耗COMS以及纳米技术蜒究的基础.确保可逆电路的正确性和可靠性,错误检测和定位必不可少.本文通过分析可逆电路发生门失效错误时对电路的影响,给出了一种门失效模型的错误定位方法,即生成错误定位树的方法.本文生成的错误定位树中,根据输入向量的不同输出能把当前错误集划分成多个小的错误集,使得树的高度较小,定位错误较快.此外,在生成电路的错误定位树时不需要生成真值表和错误表,从而节省了大量的存储空间,所以能应用于大型的电路.     

基于mRMR算法的learning-to-rank错误定位

基于learning-to-rank技术构建频谱错误定位模型,从而实现高效的程序错误定位是当前的研究热点.然而,针对不同的程序和错误类型,如何生成有效的程序频谱特征集来训练错误定位模型,成为了极具挑战的问题.针对该问题,应用mRMR算法生成程序频谱特征集,提出一种learning-to-rank的错误定位新方法.该方法应用基因编程自动生成备选可疑度公式集,并利用mRMR算法从中选取一组公式子集,该子集中的可疑度公式具有与程序错误高相关且彼此之间低相关的特性.利用此可疑度公式子集结合程序频谱计算特征值输入机器学习算法,从而构造错误定位模型.实验结果表明,新方法不仅能够提高基于learning-to-rank错误定位的效率,也优于Naish1、Tarantula等传统SBFL方法.     

一种降低NAND Flash滞留错误的纠错方案

针对NAND Flash中存在的滞留错误(Retention Error),提出了一种降低该错误的动态译码纠错方案.该方案利用系统的存储时间、擦写次数信息分析其对滞留错误造成的影响,得出了硬判决译码的最优判决电压和软判决译码的对数似然比(LLR),进而设计动态译码纠错方案.通过硬判决BCH码和软判决LDPC码对该纠错方案进行仿真验证,结果表明该方案能够有效地降低NAND Flash数据滞留引起的错误,延长数据的存储时间.     

基于Chameleon聚类分析的多错误定位方法

软件系统中往往存在多个错误,它们之间互相干扰,这抑制了错误定位的能力.为解决该问题,提出一种基于Chamelelon聚类分析的多错误定位方法.首先,将每一个失败程序执行轨迹和所有成功程序执行轨迹合并,计算其怀疑度,按怀疑度大小选取高可疑元素作为程序执行轨迹的特征元素,按照该特征元素对失败程序执行轨迹进行约简;其次,聚类分析将失败程序执行轨迹分簇,每簇包含一个错误;然后,将失败程序执行轨迹簇与所有成功程序执行轨迹合并,重新计算其怀疑度;最后,根据合并后的簇生成的怀疑度序列,采用并行调试模式同时定位程序中的多个错误.实证研究表明该方法可以有效地定位程序中的多个错误.     

基于地面加速测试的大气中子软错误率评估方法研究

大气中子单粒子效应导致的集成电路软错误给应用于地面和大气层中的具有高可靠性要求的电子系统带来了严重的失效风险,因此有必要对集成电路的大气中子软错误率进行评估.重点研究了大气中子导致的集成电路软错误的错误率的加速测试技术.首先,分别基于JESD 89A标准和EXPACS仿真工具计算了地球大气层中不同海拔处的中子通量,结果表明大气中子辐射场受海拔高度的影响非常明显;然后,以一款存储器电路为例,探讨了基于单能中子/质子源和散裂中子源的大气中子软错误率加速测试方法;最后,分别利用这两种方法对该存储器电路在海平面和飞机飞行高度处的软错误率进行了计算,飞机飞行高度处更高的软错误率表明航空飞行器面临着更严重的可靠性风险.     

一种低开销的抗SEU锁存器

随着微电子技术的不断进步,集成电路工艺尺寸不断缩小,工作电压不断降低,节点的临界电荷越来越小,空间辐射引起的单粒子效应逐渐成为影响芯片可靠性的重要因素之一。针对辐射环境中高能粒子对锁存器的影响,提出了一种低开销的抗SEU锁存器(LOHL)。该结构基于C单元的双模冗余,实现对单粒子翻转的防护,从而降低软错误发生的概率。Spice模拟结果显示,与其他相关文献中加固锁存器相比,LOHL在电路面积、延迟和延迟-功耗积上有优势。     

一种基于最弱前置条件的软件错误定位算法

错误定位是软件调试中非常耗时费力的活动之一,自动错误定位技术可以有效地提高调试效率,降低调试成本.基于最弱前置条件的错误定位技术,首先计算出程序需要满足的最弱前置条件,并为其构造错误分析图;然后在错误分析图上依照失败测试用例进行初始化标记;最后限定分析图的输入和输出,自顶向下再次对其进行标记,找到冲突的结点,从而进行错误定位.实验结果表明,相对于其它方法,文中提出的方法能有效地提高程序错误定位的效率,使得调试人员只需检查更少的语句即可找到出错的位置.     

α粒子注入对SRAM存储单元的影响研究

针对目前SRAM存储单元所面临的α粒子注入引起的软错误问题,首先采用一个简化的反相器模型,模拟其在α粒子注入时的输出变化;然后将该输出用作SRAM存储单元电路仿真的输入信号,研究α粒子注入对存储单元双稳电路稳定性的影响,其中,α粒子的注入通过一个电流源来模拟;最后,比较两种电流源模型下存储单元的存储情况。可以看出,pMOS等效电阻越大或节点电容越小,α粒子的注入越容易导致存储单元软错误的发生。也就是说,临界电荷越小,发生软错误的可能性越大。     

超深亚微米IC的宇宙射线辐射软失效研究

辐射引起的软失效一直是影响半导体可靠性的一个重大问题.特别是宇宙射线引起的在地球表面的高能中子,由于其特有的高穿透性很难有效屏蔽防护.介绍了其造成半导体器件软失效的失效机理,并利用加速软失效测试模型分别对90,65和45nm工艺的随机静态存储器的软失效率进行了分析,研究了该类中子造成的软失效率的影响因素及相关规律.据此预测了更高工艺技术产品的中子软失效率,在为芯片设计和制造阶段就对中子辐射可靠性的防护提供了一定的参考和依据.     

A cross-layer SER analysis in the presence of PVTA variations

As the technology scaling enters into the nanoscale regime, soft errors become one of the major challenging issues for VLSI chips. Susceptibility to soft error is even becoming more severe in the presence of workload-dependent Process, Voltage, Temperature, and Transistor Aging (PVTA) variations. In this paper, we propose a systematic cross-layer methodology to model and analyze the impact of different abstraction layers on the PVTA variations and in turn on the susceptibility of processors to soft error. To do so, the workload is divided into several fine-grained timing windows. Based on a top-down profiling approach, the effects of each window is projected into the circuit-level model of the processor in order to extract PVTA profiles of “each cell” in the circuit. Finally, at circuit-level, an “instance-based” simulation flow is exploited to capture both spatial and temporal PVTA-aware Soft Error Rate (SER) variations within/across applications for every functional block of the processor. The simulation results for various ITC’99 benchmark circuits and the LEON3 processor running different benchmark applications show that disregarding PVTA information results in significant error in the estimated SER.     

α粒子加速软失效率测试的稳定性研究

半导体器件软错误的发生具有几率低、间隔时间长的特点。资源有限条件的下实现对器件软失效率的评估需要借助放射源加速的方法,即加速软失效率测试。作为改进设计和工艺以降低软失效率的前提,就测试方法稳定性进行了系统研究。通过对两种不同制程的静态随机存储器芯片(SRAM)进行α粒子加速软失效率测试,提出了确保α粒子加速测试稳定的方法。基于相同测试条件下多次测量结果变化和测试时间的关系,给出了合理的加速软失效测试的时间推荐值,保证了测试结果的有效性。     

Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits

We first study the impacts of soft errors on various types of CAM for different feature sizes. After presenting a soft error immune CAM cell, SSB-RCAM, we propose two kinds of reliable CAM, DCF-RCAM and DCK-RCAM.In addition, we present an ignore mechanism to protect dual cell redundancy CAMs against soft errors. Experimental results indicate that the 11T-NOR CAM cell has an advantage in soft error immunity. Based on 11T-NOR, the proposed reliable CAMs reduce the SER by about 81% on average with acceptable overheads. The SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.     

降低亚100nm CAM电路的软错误易感性

电路的软错误易感性是VLSI设计中需要考虑的重要问题。CAM广泛应用于各种片上结构中,非常容易受软错误感染。然而,CAM的保护比其它存储元件难度更大。本文首先研究了软错误对不同类型、不同特征尺寸CAM的影响。在介绍一种软错误免疫CAM单元SSB-RCAM后,提出两种可靠CAM DCF-RCAM和DCK-RCAM。此外,本文还提出一种抛弃机制保护双单元冗余CAM免受软错误的影响。实验结果表明,11T-NOR结构的CAM单元在软错误免疫性上具有优势。基于11T-NOR结构,所提出的可靠CAM结构在可接受的开销下,平均可降低约81%的软错误率。在特定的应用中,还可以通过使用抛弃机制降低双单元冗余CAM的软错误率。     

Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit

In this work, to increase the reliability of low power digital circuits in the presence of soft errors, the use of both III-V TFET- and III-V MOSFET-based gates is proposed. The hybridization exploits the facts that the transient currents generated by particle hits in TFET devices are smaller compared to those of the MOSFET-based devices while MOSFET-based gates are superior in terms of electrical masking of soft errors. In this approach, the circuit is basically implemented using InAs TFET devices to reduce the power and energy consumption while gates that can propagate generated soft errors are implemented using InAs MOSFET devices. The decision about replacing a subset of TFET-based gates by their corresponding MOSFET-based gates is made through a heuristic algorithm. Furthermore, by exploiting advantages of TFETs and MOSFETs, a hybrid TFET-MOSFET soft-error resilient and low power master-slave flip-flop is introduced. To assess the efficacy of the proposed approach, the proposed hybridization algorithm is applied to some sequential circuits of ISCAS’89 benchmark package. Simulation results show that the soft error rate of the TFET-MOSFET-based circuits due to particle hits are up to 90% smaller than that of the purely TFET-based circuits. Furthermore, energy and leakage power consumptions of the proposed hybrid circuits are up to 79% and 70%, respectively, smaller than those of the MOSFET-only designs.     

Designing robust threshold gates against soft errors

In applications where issues like power efficiency, high performance, and more noise tolerance are important, asynchronous design methodology can play a significant role. However, as a result of technology shrinkage, combinational asynchronous circuits have become vulnerable in presence of particle strikes. In this paper, we design robust quasi-delay insensitive (QDI) asynchronous circuits against soft errors. Null Convention Logic (NCL) gates used as one of the basic techniques in asynchronous circuits, are redesigned to increase their robustness against Single Event Upset (SEU). We analyze our design for various NCL structures and compare them with another design in Kuang et al. (2007) [4], and show that our proposed approach is more robust against SEU. The effect of some parameters such as power consumption, delay, and the influence of transistor sizing on soft error tolerance are discussed.     

A practical metric for soft error vulnerability analysis of combinational circuits

Besides the advantages brought by technology scaling, soft errors have emerged as an important reliability challenge for nanoscale combinational circuits. Hence, it is important for vulnerability analysis of digital circuits due to soft errors to take advantage of practical metrics to achieve cost-effective and reliable designs. In this paper, a new metric called Triple Constraint Satisfaction probability (TCS) is proposed to evaluate the soft error vulnerability of combinational circuits. TCS is based on a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for soft-error occurrence in the circuit. We propose a computation model to calculate the PVW’s for all circuit gate outputs. In order to show the efficiency of the proposed metric, TCS is used in the vulnerability ranking of the circuit gates as the basic step of the vulnerability reduction techniques. The experimental results show that TCS provides a distribution of soft error vulnerability similar to that obtained with fault injections performed with HSPICE or with an event driven simulator while it is more than three orders of magnitude faster. Also, the results show that using the proposed metric in the well-known filter insertion technique achieves up to 19.4%, 34.1%, and 55% in soft error vulnerability reduction of benchmark circuits with the cost of increasing the area overhead by 5%, 10%, and 20%, respectively.     

Node-to-node error sensitivity analysis using a graph based approach for VLSI logic circuits

Shrinking the transistors size and supply voltage in the advanced VLSI logic circuits, significantly increases the susceptibility of the circuits to soft errors. Therefore, analysis of the effects on other nodes, caused by the soft errors occurring at each individual node is an essential step for VLSI logic circuit design. In this paper, a novel approach based on the Mason’s gain formula, for the node-to-node sensitivity analysis of logic circuits is proposed. Taking advantage of matrix sparsity, the runtime and the memory requirement of the proposed approach become scalable. Also, taking the effects of reconvergent paths into account, the accuracy of the proposed approach is improved considerably. According to the simulation results, the proposed approach runs 4.7× faster than those proposed in the prior works while its computational complexity is O(N^1.07) on the average.     

光纤陀螺漂移误差动态Allan方差分析

提出采用动态Allan方差(DAVar,Dynamic Allan variance)方法对光纤陀螺实测数据进行分析,系统地分析了引起光纤陀螺漂移误差的随机噪声种类及其来源和特性,DAVar分析方法的优势在于不仅能确定各种随机漂移的系数,而且可以跟踪和描述信号随时间变化的稳定性.实验证明,DAVar分析是对光纤陀螺随机漂移进行研究的有效方法.