基于PCRAM数据页聚簇的缓冲算法

针对Flash写前需擦除,读写I/O开销不均衡等固有缺陷,研究面向闪存缓冲区管理,对提高基于Flash的固态硬盘(Solid State Disk,SSD)访问性能以及降低系统功耗具有重要理论意义和应用价值。文章提出了一种新型存储架构,并实现了一种适用于SSD的基于相变存储器(Phase Change Memory,PCRAM)数据页聚簇的缓冲算法。文章中详细介绍了基于PCRAM聚簇的缓冲算法关键技术及原理,充分阐述算法相关元数据、存储数据、FTL管理与控制以及详尽分析了缓冲算法的读、写操作控制原理,最后通过FlashSim仿真平台实现SSD写缓冲。基于仿真结果与传统缓冲算法性能比对,分析得出该缓冲算法可降低SSD随机写次数和SSD数据存储分散性,并提升SSD响应速度,降低系统功耗。     

一种高速数据采集记录装置的设计

文章介绍了一种基于Flash的高速数据采集记录装置的实现方案;文中采用了Flash高速存储技术与FPGA的二级缓冲技术,提高了存储速度,突破存储芯片的瓶颈,成功实现了数据存储速率与传输速率完美的匹配;同时通过设计合理的电路降低了存储模块的功耗,利用可靠的通信协议,有效保证了信号数据的可靠接收和存储。     

一种NAND Flash动态坏块管理算法的设计与实现

文章针对NAND Flash在大容量数据存储时对可靠性的要求,提出一种基于逻辑一物理块地址映射表的大容量NAND Flash动态坏块管理算法。该方法可彻底屏蔽对坏块的操作,实现对NAND Flash的有效存储,具有较高的实际应用价值。     

基于多核处理器的安全固态硬盘实现技术

固态硬盘（Solid State Disk,SSD）主要由硬盘控制芯片和存储芯片构成，利用传统的NAND Flash特性，以区块写入和擦除的方式进行读写。基于闪存颗粒的固态硬盘具有功耗低、体积小、性能快、稳定性好等特点，广泛用于各类型移动作业领域。出于对数据存储领域存在的各种安全问题现状的考虑，提出并实现了一种基于多核处理器盘控芯片的固态硬盘全盘加密存储、安全启动新技术，该技术使用国密SM2、SM3、SM4算法，与整机BIOS弱耦合，采用安全配置管理工具进行管控，具有安全性强、自主可控、可扩展性强等优点，具有很好的市场前景。     

串行Flash在图像存储系统中的应用

介绍串行SPI接口Flash存储器M25P64的工作原理,利用该Flash作为FPGA的代码配置芯片,同时用作图像存储系统的存储器.在图像采集系统中,利用DDR SDRAM存储器作为帧缓存,将需要存储的图像先写入DDR存储器,写入一帧图像后,从DDR中每次连续读出一行图像数据至Flash写缓冲,经Flash控制器模块写...     

面向大型发电设备的数据高速存储与智能化分析技术研究

针对双塔双循环脱硫系统耗电量高的问题,提出了基于数据高速存储与智能化分析的脱硫系统优化运行方法。该方法构建了面向大型发电设备的高速存储数据架构,包括数据采集、数据处理、数据存储、数据管理、数据诊断和数据展示共6个模块。其利用机组实时负荷、目标负荷与负荷变化率等数据,采用长短期记忆（LSTM）算法预测系统实时工况下的入口SO2浓度和SO2脱除量。同时,基于对机组负荷、浆泵组合、浆液pH值、SO2入口浓度等历史数据的分析,通过层次凝聚聚类（HAC）算法构建样本数据库,并将系统实时工况数据与样本数据库进行精准匹配,以实现工况寻优。以某发电厂的脱硫系统进行数据仿真验证的结果表明,所提运行优化方法能够精准地调整浆泵组合运行方式,降低系统运行成本,并提高系统脱硫效率。     

基于相似度加速的自适应聚类联邦学习

为了解决联邦学习过程中数据异质性导致模型性能下降的问题,考虑对联邦模型个性化,提出了一种新的基于相似度加速的自适应聚类联邦学习（ACFL）算法,基于客户端本地更新的几何特性和客户端联邦时的正向反馈实现自适应加速聚类,将客户端划分到不同任务簇,同簇中数据分布相似的客户端协同实现聚类联邦学习（CFL）,从而提升模型性能。该算法不需要先验确定类簇数量和迭代划分客户端,在避免现有基于聚类的联邦算法计算成本过高、收敛速度慢等问题的同时保证了模型性能。在常用数据集上使用深度卷积神经网络验证了ACFL的有效性。结果表明,所提算法性能与聚类联邦学习算法相当,优于传统的迭代联邦聚类算法（IFCA）,且具有更快的收敛速度。     

基于PCRAM主存系统的访问机制

随着基于DRAM主存系统功耗的不断上升,相变随机访问存储器(PCRAM)凭借其高密度、低功耗、非易失等优点,将成为下一代最有潜力的主存技术.然而,PCRAM的写操作具有寿命有限和写入能耗、延时较大的特点,限制了其在主存系统中的应用.为了延长主存系统的使用寿命并减少写入能耗,采用写前读技术设计了一种基于异或的数据并行机制.实验结果表明,经过该机制处理,与传统的Data Comparison Write和Flip-N-Write机制相比,写寿命分别延长38%和19%,写入能耗分别减少28%和17%.     

全数字ADC设计与仿真

微电子系统的全数字化集成旨在降低工艺成本。基于全数字CMOS门技术设计实现的ADC芯片,具有功耗低的特点,原理分类为压控振荡与并行神经网络两大类。区别于非门环路振荡技术,我们选择施密特非门振荡器实现压频转换模块,仿真该模块的频率、温度、功耗以及后续计数编码的位宽等指标。研究结果是该模块具有良好的温度适应能力（0.187Hz/℃）和超低功耗（400μW）等优点。本工作为准全数字化ADC设计仿真贡献了实验数据积累。     

基于NAND Flash的存储设备设计与实现

Flash是目前最火的存储介质,具有传输速度快、功耗小、无噪音等优点。但用于存储设备时常因片上总线的局限而性能低下。针对因总线限制Flash性能发挥的问题,设计了一种基于AXI总线的NAND Flash存储设备,所设计的存储设备具有多通道传输、流水线操作、ECC校验,以及RAID5架构存储等功能。设计分析与测试结果表明,设计的基于NAND Flash存储系统传输速度更快,系统更稳定,同时增强了存储数据的可靠性为NAND Flash存储设备的研究提供了一个新的解决方案。     

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%–50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.      

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.     

Lazy-split B+-tree: a novel B+-tree index scheme for flash-based database systems

Flash memory is rapidly being deployed as a data storage medium for embedded systems and tablet computers due to its shock resistance, fast access, and low power consumption, etc. However, it has some intractable characteristics, such as erase-before-write, asymmetric read/write/erase speed, and a limited number of write/erase cycles. Due to these hardware limitations, magnetic disk-based systems and applications can hardly make full use of the advantages of flash memory when adopting it directly for storage. For example, the frequent changes of B-tree can degrade the performance and negatively influence the lifespan of flash memory. Most state-of-the-art studies on flash-aware index design focused mainly on buffer and storage mechanisms whereby they can obtain efficient I/Os to flash memory. In this paper, we identify the problems inherent in the related studies, and then introduce the concepts of lazy-split, modify-two-node, and semi-clean, which make possible the construction of a novel index solution, the Lazy-Split B⁺-tree (LSB⁺-tree). In detail, by their introduction, the first concept of LSB⁺-tree can efficiently reduce the number of node splits, the second can reduce the number of node modifications, and the last can make a further improvement on buffer space utilization and flash writes reduction.     

Energy-Aware Flash Memory Management in Virtual Memory System

The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for many portable devices with the continuing improvements on its capacity, reliability and much lower power consumption than mechanical hard drives. The characteristics of flash memory are quite different from a magnetic disk. Therefore, in this paper, we revisit virtual memory system design considering limitations imposed by flash memory. In particular, we focus on the energy efficient aspect since power is the first-order design consideration for embedded systems. Due to the write-once feature of flash memory, frequent writes incur frequent garbage collection thereby introducing significant energy overhead. Therefore, in this paper, we propose three methods to reduce writes to flash memory. The HotCache scheme adds an SRAM cache to buffer frequent writes. The subpaging technique partitions a page into subunits, and only dirty subpages are written to flash memory. The duplication-aware garbage collection method exploits data redundancy between the main memory and flash memory to reduce writes incurred by garbage collection. We also identify one type of data locality that is inherent in accesses to flash memory in the virtual memory system, intrapage locality. Intrapage locality needs to be carefully maintained for data allocation in flash memory. Destroying intrapage locality causes noticeable increases in energy consumption. Experimental results show that the average energy reduction of combined subpaging, HotCache, and duplication-aware garbage collection techniques is 42.2%.     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

一种基于差分进化的Flash文件系统垃圾回收算法

垃圾回收算法对于Flash文件系统具有十分重要的意义.本文针对已有垃圾回收算法在存储容量剩余较小时垃圾回收性能急剧下降进而影响写入速率的问题,采用最优化方法,提出并实现了一种基于差分进化的垃圾回收算法.该算法能够使得垃圾回收的代价均匀化,在保证性能和损耗均衡的前提下,减少擦除次数,延长Flash寿命.实验结果验证了该算...     

WSN中一种基于LEACH的协同通信算法的研究

近年来,协同通信在无线传感器网络中取得了很大的应用,重点分析和研究了一种基于低功耗自适应集簇分层型协议（LEACH）的协同通信算法;在该算法中,通过选择合适的协同节点来发送数据可以有效的减少簇头节点的能量消耗,并且与多跳传输相比,又节省了路由更新耗费的能量,实验仿真证明基于LEACH的协同算法（LEACH-COOP）在能量消耗上与LEACH和基于LEACH的簇头多跳算法（LEACH-MH）相比表现出了更优的性能。     

Embedded compact flash

A new data storage system designed for a data acquisition system is presented. The article describes the architecture of a large non-volatile memory data storage system (DSS) mainly developed for compact flash (CF) memory. A DSS handles the available storage space of the medium as a circular buffer rather than as an emulated disk in order to provide an efficient and easy to use software interface. A circular buffer is simply another name for a first-in-first-out (FIFO) buffer. The name circular buffer helps to visualize the wraparound condition. CF memories provide a persistent storage medium using solid-state memory technology at a lower cost and lower power consumption than other solid-state technologies.     

基于单片机的大容量静态存储器接口设计

为解决采集系统中大量数据存储及数据传输问题,对数据采集系统中基于单片机大容量静态存储器的应用进行了刨析。闪速存储器采用Atmel公司的AT29C040,对系统的总体设计思想及闪速存储器的特点做了阐述。给出了基于8位单片机进行4Mb高速存储器扩展的具体接口电路及其驱动程序。该系统具有在掉电情况下保存数据的功能,且具有存储数据容量大,体积小,功耗低,数据保存安全可靠等特点,适合于便携式流动性环境下的数据采集系统。     

基于龙芯3A的低功耗存储控制器的研发

云计算和物联网时代的一个重要特点是信息数据量爆炸性增长。图灵奖获得者Jim Gray提出了一个经验定律,每18个月的数据量是有史以来数据量的总和,存储控制器是管理这些海量数据的中枢。存储控制器对主处理器的性能要求很高,尤其是I/O吞吐性能,目前中高端存储控制器采用功耗大、接口复杂的主处理器,造成整机功耗大、系统电路复杂等问题。龙芯3A处理器较好的解决了功耗问题,为高性能低功耗存储控制器的研发提供了可能。本文研究基于龙芯3A构架的低功耗存储控制器硬件设计、基于缓存算法的读写性能提升。