Structural and interfacial properties of high-k HfOxNy gate dielectric films

The thermal stability and interfacial characteristics for hafnium oxynitride (HfO_xN_y) gate dielectrics formed on Si (1 0 0) by plasma oxidation of sputtered HfN films have been investigated. X-ray diffraction results show that the crystallization temperature of nitrogen-incorporated HfO₂ films increases compared to HfO₂ films. Analyses by X-ray photoelectron spectroscopy confirm the nitrogen incorporation in the as-deposited sample and nitrogen substitution by oxygen in the annealed species. Results of FTIR characterization indicate that the growth of the interfacial SiO₂ layer is suppressed in HfO_xN_y films compared to HfO₂ films annealed in N₂ ambient. The growth mechanism of the interfacial layer is discussed in detail.     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Characterization of various alloying metal oxide nanoparticles embedded in HfOxNy as charge trapping nodes in nonvolatile memory devices

This work compares Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO alloying metal oxide nanoparticles (AMONs) that were individually embedded in HfO_xN_y high-k dielectric as charge trapping nodes. They were formed by chemical vapor deposition using Co/Mo, Co/Fe and Fe/Mo acetate, respectively, calcined and reduced in Ar/NH₃ ambient. The effects of various pre-treatments on Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO AMONs preparation were investigated. The results indicate that the larger charge trap density, larger memory window and better programming characteristics of Co_xMo_yO AMONs are attributable to their higher surface density and smaller diameter. The average collected charge in each Co_xMo_yO AMON is the smallest among three AMONs, revealing that a local leakage path is associated with the least charge loss. The main mechanism that governs the programming characteristics involves the trapping of holes.     

Control of Interface Traps in HfO2 Gate Dielectric on Silicon

The effects of postdeposition annealing (PDA) on the interface between HfO₂ high-k dielectric and bulk silicon were studied in detail. The key challenges of successfully adopting the high-k dielectric/Si gate stack into advanced complementary metal–oxide–semiconductor (CMOS) technology are mostly due to interfacial properties. We have proposed a PDA treatment at 600°C for several different durations (5 min to 25 min) in nitrogen or oxygen (95% N₂ + 5% O₂) ambient with a 5-nm-thick HfO₂ film on a silicon substrate. We found that oxidation of the HfO₂/Si interface, removal of the deep trap centers, and crystallization of the film take place during the postdeposition annealing (PDA). The optimal PDA conditions for low interface trap density were found to be dependent on the PDA duration. The formation of an amorphous interface layer (IL) at the HfO₂/Si interface was observed. The growth was due to oxygen incorporated during thermal annealing that reacts with the Si substrate. The interface traps of the bonding features, defect states, and hysteresis under different PDA conditions were studied using x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), transmission electron microscopy (TEM), and leakage current density–voltage (J–V) and capacitance–voltage (C–V) techniques. The results showed that the HfO₂/Si stack with PDA in oxygen showed better physical and electrical performance than with PDA in nitrogen. Therefore, PDA can improve the interface properties of HfO₂/Si and the densification of HfO₂ thin films.     

Process integration of Pr-based high-k gate dielectrics

We present the process integration of the Pr-based high-k oxides Pr₂O₃, PrTi_xO_y and Pr_xSi_yO_z for CMOS devices. MOS structures were grown in form of p⁺ poly-Si/Pr-based dielectric/Si(100) by MBE. RIE with CF₄/O₂ plasma was used to selectively remove the poly-Si layer. It was found that the Pr-based oxides layers can be dissolved with high selectivity in diluted H₂SO₄ solutions. Details of the etch kinetics of Pr-based oxides and poly-Si were studied. Electrical characteristics of MOS stacks with integrated Pr_xSi_yO_z are presented.     

Electrodepositing ZnxMnyOz alloys from zinc oxide to manganese oxide

Electrodeposition has emerged as a practical and simple method to synthesise semiconductor materials under different forms, thin films or nanostructured layers. This work reports on the cathodic electrodeposition of ZnMnO thin layers using both zinc and manganese chlorides as precursors. The composition of thin films can be varied from binary zinc oxide to manganese oxide varying the Mn/(Mn+Zn) ratio between 0 and 1. The composition of Zn_xMn_yO_z films was obtained by energy dispersive spectroscopy. Zn_1−xMn_xO films with Mn/Zn ratio less than 10% exhibit a crystalline wurtzite structure typical of ZnO fully oriented in the (0 0 2) direction. Higher Mn content leads to deformation of the ZnO lattice and the wurtzite structure is no longer maintained. X-ray photoelectron spectroscopy points out that Mn₃O₄ tends to be deposited when a high Mn/Zn ratio is used in the starting solution. Magnetic measurements on films with Mn/(Zn+Mn) ratio near 1 reveal magnetic characteristics similar to Mn₃O₄ compounds. The transmission spectra of Zn_xMn_yO_z show the typical absorption edge of crystalline ZnO while the wurtzite structure is maintained and it shifts to higher wavelengths when Mn content increases.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Resistance switching in HfO2-based OxRRAM devices

We have investigated the origins of the resistivity change during the forming of HfO₂ based resistive random access memories. The high and low resistive states of HfO₂ were investigated using electrical measurements, TEM, XPS, and AES. TEM and XPS show that the HfO₂/TiN interface is free from TiO_xN_y oxi-nitride states. Electrical measurements show that voltage threshold magnitude required for the formation of the conductive paths through the HfO₂ layer depends on the polarity. The AES measurements show that HfO₂ and HfO_x or Hf metallic may coexist in the low resistive state.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate

Strained SiGe quantum well p-MOSFETs with LaLuO₃ higher-k dielectric were fabricated and characterized. The strained Si/strained Si_0.5Ge_0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an I_on/I_off ratio of 10⁵. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO₂ or even SiO₂ gate dielectric devices.     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.     

Resistive switching characteristics of ultra-thin TiOx

We investigated the resistive switching characteristics of Ir/TiO_x/TiN structure with 50 nm active area. We successfully formed ultra-thin (4 nm) TiO_x active layer using oxidation process of TiN BE, which was confirmed by X-ray Photoelectron Spectroscopy (XPS) depth profiling. Compared to large area device (50 μm), which shows only ohmic behavior, 250 and 50 nm devices show very stable resistive switching characteristics. Due to the formation and rupture of oxygen vacancies induced conductive filament at Ir and TiO_x interface, bipolar resistive switching was occurred. We obtained excellent switching endurance up to 10⁶ times with 100 ns pulse and negligible degradation of each resistance state at 85 °C up to 10⁴ s.     

Formation of Ni(Ge1−xSnx) layers with solid-phase reaction in Ni/Ge1−xSnx/Ge systems

We have demonstrated the formation of Ni(Ge_1−ySn_y) layers on Ge_1−xSn_x layers by using solid-phase reaction for samples with Sn contents ranging from 2.0% to 6.5%. We have also investigated solid-phase reaction products in Ni/Ge_1−xSn_x/Ge samples after annealing and the crystalline properties of nickel-tin-germanide layer/Ge_1−xSn_x contact structures. After annealing at temperatures ranging from 350 to 550 °C, the formation of polycrystalline Ni(Ge_1−ySn_y) layers has been observed on epitaxial Ge_1−xSn_x layers with Sn contents ranging from 2.0% to 6.5%. We also observed anisotropic crystal deformation of NiGe with the incorporation of Sn atoms into substitutional sites in NiGe. In the case of the Ni/Ge_1−xSn_x/Ge sample with a Sn content of 3.6%, the formation of an epitaxial Ni₂(Ge_1−zSn_z) layer on the Ge_1−xSn_x layer was found. The formation of β-Sn crystallites was observed after annealing at above 450 °C in samples with a high Sn content of 6.5%. This β-Sn formation is due to the precipitation of Sn atoms. In all samples annealed at 350 °C, the morphology of Ni-Ge-Sn layers is smooth and uniform. However, the surface roughness and interface roughness increase for an annealing temperature of 550 °C. In particular, in the sample with a Sn content of 6.5%, the temperature at which agglomeration noticeably occurs is as low as 450 °C.     

Chemical compositions and optical properties of HfOxNy thin films at different substrate temperatures

High-k HfO_xN_y thin films have been grown by radio frequency (rf) reactive sputtering of metal Hf target in N₂/Ar/O₂ ambient at different substrate temperatures. The chemical compositions of the films have been investigated as a function of substrate temperature by X-ray photoelectron spectroscopy (XPS). XPS measurements showed that nitrogen concentration increases with an increase in substrate temperature. Room-temperature spectroscopic ellipsometry (SE) with photon energy 0.75–6.5 eV was used to investigate the optical properties of the films. SE results demonstrated that refractive index n increases with an increase in substrate temperature. Based on TL parameters which were obtained from the best fit results used in a simulation of the measured spectra, meanwhile, we conclude that the energy band gap (E_g) decreases with an increase in substrate temperature.     

Temperature and annealing effects on InAs nanowire MOSFETs

We report on temperature dependence on the drive current as well as long-term effects of annealing in vertical InAs nanowire Field-Effect Transistors. Negatively charged traps in the HfO₂ gate dielectric are suggested as one major factor in explaining the effects observed in the transistor characteristics. An energy barrier may be correlated with an un-gated InAs nanowire region covered with HfO₂ and the effects of annealing may be explained by changed charging on defects in the oxide. Initial simulations confirm the general effects on the I-V characteristics by including fixed charge.     

Determination of boron concentration in heavily doped p-type Si1−xGex/Si heterostructure by infrared ellipsometric spectroscopy

Si_1−xGe_x/Si heterostructures play a primary role in the Si-based fast electronics developments of today. In this work, we will present the experimental results of infrared spectroscopic ellipsometry (IRSE) for structural determination of the boron heavily doped SiGe/Si sample grown by ultra-high vacuum chemical vapor deposition (UHVCVD) (the Ge atomic percent, the thickness of SiGe film and boron concentration). Especially, the principle of boron concentration in p-type SiGe film layer determined by IRSE was elucidated in detail. In addition, in order to corroborate the validity of IRSE for determining dopant concentration, secondary ion mass spectroscopy (SIMS) experiment has also been carried out. The close experimental agreement between IRSE and SIMS demonstrate that IRSE as a contactless, and non-destructive technology can be used in-line tools in production used for measuring the Ge content, the thickness of SiGe layer and boron concentration in p-type dopant SiGe/Si heterostructure, which often used the base layer of SiGe hetero-junction bipolar transistor (HBT) devices.     

低温退火对具有HfO2/TiN栅结构的MOS电容电学性能的影响

The effects of low temperature annealing,such as post high-k dielectric deposition annealing(PDA),post metal annealing(PMA)and forming gas annealing(FGA)on the electrical characteristics of a metal–oxide–semiconductor(MOS)capacitor with a TiN metal gate and a HfO2dielectric are systematically investigated.It can be found that the low temperature annealing can improve the capacitance–voltage hysteresis performance significantly at the cost of increasing gate leakage current.Moreover,FGA could effectively decrease the interfacial state density and oxygen vacancy density,and PDA could make the flat band positively shift which is suitable for P-type MOSs.