基于SCA软件无线电的数字中频系统设计

数字中频是软件无线电平台的核心组成部分,对A/D,D/A性能有很高的要求.根据软件无线电SCA规范,在已有的基带系统基础上,通过对器件选型、参数设定、滤波器设计等关键部分的详细分析,设计了一套与之匹配的数字中频系统,主要包括AD6645完成模数转换,AD9772A完成数模转换,以及CDCM7005专用时钟芯片为各部分提...     

带有多种参数输出的测试装置

介绍了带液晶显示的多参数输出测试装置，该系统由89C52微处理器和12位A／D转换芯片AD574及12位D／A转换芯片AD7522实现，并带有RS—232通信接口和CAN总线，便于组成DCS或FCS系统。     

一种高性能D／A转换器在雷达中的应用分析

介绍了D／A转换器AD9777芯片的功能特点以及系统结构特点，采用FPGA控制AD9777，实现了宽带线性调频信号的产生，最后与采用AD9764实现方法进行了对比。     

AD9873在宽带有线电视机顶盒中的应用

AD9873是用于彬模和模／数转换的芯片，它带有1个D／A和4个A／D通道，用于对各种不同的混合信号进行处理和传输。该芯片可用于电缆调制解调器、数字通信、数据和视频调制解调器等。介绍AD9873的工作特点与性能参数，以及它在数字电视机顶盒中的应用。     

基于ADμC812的在系统可编程数据采集电路的设计

介绍了ADI公司的MCS51系列单片机的兼容芯片ADμC812，并基于该芯片设计了一种具有在系统可编程能力的数据采集电路。该数据采集电路采用ADμC812的片内A／D和D／A转换器减小了电路体积；同时应用这种芯片的在系统可编程能力不仅可以方便地在应用现场对系统进行升级，而且在设计调试阶段不需要专用硬件开发设备和编程设备的支持。     

高性能A／D芯片AD9203与ADSP2191的高速DMA通信

文章对高速的10位A/D芯片AD9203进行了全面介绍，并结合ADSP219l的DMA高速数据传输模式，给出了AD9203与ADS2191两种DMA方式下的通信接口电路。     

A／D转换器AD574及其应用

本文介绍了A／D转换器AD574的工作原理,叙述了芯片各管脚的功能,提出了芯片应用时的注意事项。     

基于AD9244和PCI总线的数据采集方案

介绍在虚拟接收机的研究背景下，基于AD9244和PCI总线实现的数据采集系统。AD9244．是黄国ADI公司推出的一种14住、低功耗A／D转换芯片。整个系统采用CPLD作为逻辑控制，两片IDT7204芯片构成14位4kbit容量的缓存器。     

AD9883在平板显示视频接口中的应用

结合平板显示器（FPD）视频显示的原理，介绍了平板显示器接口芯片AD9883的主要性能。重点论述了芯片功能结构、内部寄存器设置以及在平板显示视频接口中的应用。结合FPGA技术提出了一种接口电路方案，实现高分辨率视频图像的采集，为平板显示器件提供良好的数字视频源。利用AD9883高速、高精度的视频A／D转换功能，该方案支持显示分辨率最高为SXGA，可广泛应用于多种平板显示器件。     

DVB—S信道调制器的FPGA实现

针对DVB-S标准，采用Xilinx公司XC3S500E芯片与AD9775D／A芯片相结合的架构，通过Verilog HDL语言对信道编码及QPSK部分进行设计、仿真与实现，符合DVB-S标准要求，为DVB-S调制器设计提供了一种新颖并且简便可行的设计方案。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.