Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

High-performance double-recessed enhancement-mode metamorphic HEMTs on 4-in GaAs substrates

Enhancement-mode InAlAs/InGaAs/GaAs metamorphic HEMTs with a composite InGaAs channel and double-recessed 0.15-/spl mu/m gate length are presented. Epilayers with a room-temperature mobility of 10 000 cm/sup 2//V-s and a sheet charge of 3.5/spl times/10/sup 12/cm/sup -2/ are grown using molecular beam epitaxy on 4-in GaAs substrates. Fully selective double-recess and buried Pt-gate processes are employed to realize uniform and true enhancement-mode operation. Excellent dc and RF characteristics are achieved with threshold voltage, maximum drain current, extrinsic transconductance, and cutoff frequency of 0.3 V, 500 mA/mm, 850 mS/mm, and 128 GHz, respectively, as measured on 100-/spl mu/m gate width devices. The load pull measurements of 300-/spl mu/m gate width devices at 35 GHz yielded a 1-dB compression point output power density of 580 mW/mm, gain of 7.2 dB, and a power-added efficiency of 44% at 5 V of drain bias.     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.     

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.     

Nonalloyed ohmic contacts in AlGaN/GaN HEMTs by ion implantation with reduced activation annealing temperature

This letter reports AlGaN/GaN high-electron mobility transistors with capless activation annealing of implanted Si for nonalloyed ohmic contacts. Source and drain areas were implanted with an Si dose of 1/spl times/10/sup 16/ cm/sup -2/ and were activated at /spl sim/1260/spl deg/C in a metal-organic chemical vapor deposition system in ammonia and nitrogen at atmospheric pressure. Nonalloyed ohmic contacts to ion-implanted devices showed a contact resistance of 0.96 /spl Omega//spl middot/mm to the channel. An output power density of 5 W/mm was measured at 4 GHz, with 58% power-added efficiency and a gain of 11.7 dB at a drain bias of 30 V.     

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.     

Carrier mobility in MOSFETs fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrode, and self-aligned source and drain

A study of electron and hole mobilities for MOSFET devices fabricated with Hf-Si-O-N gate dielectric, polysilicon gate electrodes and self-aligned source and drain is presented. High effective electron and hole mobilities, 250 cm/sup 2//V/spl middot/s and 70 cm/sup 2//V/spl middot/s, respectively, were measured at high effective field (>0.5 MV/cm). The NMOSFETs have an equivalent oxide thickness (EOT) of 1.3 nm and the PMOSFETs have an EOT of 1.5 nm. The effect of interface engineering on the electron and hole mobilities is discussed.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

8.5 m/spl Omega/ /spl middot/ cm/sub 2/ 600-V double-epitaxial MOSFETs in 4H-SiC

The most important issue in realizing a 4H-SiC vertical MOSFET is to improve the poor channel mobility at the MOS interface, which is related to high on-resistance. This letter focuses on a novel 4H-SiC vertical MOSFET device structure where a low acceptor concentration epitaxial layer is used as a channel. We call this structure a double-epitaxial MOSFET (DEMOSFET). In the structure, the p-well is composed of two p-type epitaxial layers, while an n-type region between the p-wells is formed by low-dose n-type ion implantation. A buried channel is formed at the surface of the upper p/sup $/epitaxial layer. A fabricated DEMOSFET showed an on-resistance of 8.5 m/spl Omega//spl middot/cm/sup 2/ at a gate voltage of 15 V and a blocking voltage of 600 V. This on-resistance is the lowest so far reported for a vertical MOSFET with a blocking voltage of 600 V.     

Top-gate TFTs using 13.56 MHz PECVD microcrystalline silicon

Top-gate thin-film transistors (TFTs) with microcrystalline silicon (/spl mu/c-Si) channel layers deposited using standard 13.56 MHz plasma-enhanced chemical vapor deposition were fabricated at a maximum processing temperature of 250/spl deg/C. The TFTs employ amorphous silicon nitride (a-SiN) as the gate dielectric layer. The 80-nm-thick /spl mu/c-Si channel layer showed a dark conductivity of the order of 10/sup -7/ S/cm and a crystalline volume fraction of over 80%. The /spl mu/c-Si TFTs showed a field effect mobility of 0.85 cm/sup 2//V/spl middot/s, a threshold voltage of 4.8 V, a subthreshold slope of 1 V/dec, and an ON/OFF current ratio of /spl sim/10/sup 7/. More importantly, the TFTs were very stable under gate bias stress, offering promise for organic light-emitting display (OLED) applications.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.     

Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 /spl times/ 64 pixel (300 /spl mu/m pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm/sup 2//V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/.     

Submicron AlGaN/GaN HEMTs with very high drain current density grown by plasma-assisted MBE on 6H-SiC

High electron mobility transistors (HEMTs) were fabricated from AlGaN/-GaN layers grown by plasma-assisted molecular beam epitaxy on semi-insulating 6H-SiC substrates. Room-temperature Hall effect measurements yielded a polarization-induced 2DEG sheet charge of 1.3/spl middot/10/sup 13/ cm/sup -2/ and a low-field mobility of 1300 cm/sup 2//V/spl middot/s. Submicron gates were defined with electron beam lithography using an optimized two-layer resist scheme. HEMT devices repeatedly yielded drain current densities up to 1798 mA/mm, and a maximum transconductance of 193 mS/mm. This is the highest drain current density in any AlGaN-GaN HEMT structure delivering significant microwave power reported thus far. Small-signal testing of 50-/spl mu/m wide devices revealed a current gain cutoff frequency f/sub T/ of 52 GHz, and a maximum frequency of oscillation f/sub max/ of 109 GHz. Output power densities of 5 W/mm at 2 GHz, and 4.9 W/mm at 7 GHz were recorded from 200-/spl mu/m wide unpassivated HEMTs with a load-pull setup under optimum matching conditions in class A device operation.     

High-performance ultralow-temperature polycrystalline silicon TFT using sequential lateral solidification

This letter presents technologies to fabricate ultralow-temperature (< 150 /spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT). Sequential lateral solidification is used for crystallization of RF magnetron sputter deposited amorphous silicon films resulting in a high mobility polycrystalline silicon (poly-Si) film. The gate dielectric is composed of plasma oxidation and Al/sub 2/O/sub 3/ grown by plasma-enhanced atomic layer deposition. The breakdown field on the poly-Si film was above 6.3 MV/cm. The fabricated ULTPS TFT showed excellent performance with mobility of 114 cm/sup 2//V /spl middot/ s (nMOS) and 42 cm/sup 2//V /spl middot/ s (pMOS), on/off current ratio of 4.20 /spl times/ 10/sup 6/ (nMOS) and 5.7 /spl times/ 10/sup 5/ (pMOS), small V/sub th/ of 2.6 V (nMOS) and -3.7 V (pMOS), and swing of 0.73 V/dec (nMOS) and 0.83 V/dec (pMOS).