不用大尺寸掩膜版的曝光机

V．Tech．公司开发了6、7代TFT-LCD生产线的不用大尺寸掩膜版的曝光机。该曝光设备只要设定基板第一层的图形之后，在不使用大尺寸掩膜版的情况下能够完成后面工序的曝光工艺；同时具有图形监测系统和许多个曝光光源，以及在基板移动方向上约5cm宽度的形成图形的掩膜版装置，可边移动基板边曝光，     

SAL601负性电子束抗蚀剂纳米级集成电路加工

讨论了采用SAL601负性化学放大电子柬抗蚀剂进行电子束曝光应用于纳米级集成电路加工的实验方法与工艺条件。经过大量实验总结，通过变剂量模型对电子束曝光中电子散射参数进行提取，应用于邻近效应校正软件，针对集成电路曝光图形进行邻近效应校正。校正后的曝光图形经过曝光实验确定显影时间及曝光剂量，最终得到重复性良好的，栅条线宽为70nm的集成电路曝光图形。     

SAL601负性电子束抗蚀剂纳米级集成电路加工

讨论了采用SAL6 0 1负性化学放大电子束抗蚀剂进行电子束曝光应用于纳米级集成电路加工的实验方法与工艺条件。经过大量实验总结 ,通过变剂量模型对电子束曝光中电子散射参数进行提取 ,应用于邻近效应校正软件 ,针对集成电路曝光图形进行邻近效应校正。校正后的曝光图形经过曝光实验确定显影时间及曝光剂量 ,最终得到重复性良好的 ,栅条线宽为 70nm的集成电路曝光图形     

SAL601负性电子束抗蚀剂纳米级集成电路加工

讨论了采用SAL601负性化学放大电子束抗蚀剂进行电子束曝光应用于纳米级集成电路加工的实验方法与工艺条件.经过大量实验总结,通过变剂量模型对电子束曝光中电子散射参数进行提取,应用于邻近效应校正软件,针对集成电路曝光图形进行邻近效应校正.校正后的曝光图形经过曝光实验确定显影时间及曝光剂量,最终得到重复性良好的,栅条线宽为70nm的集成电路曝光图形.     

电子束曝光中的邻近效应修正技术

邻近效应是指电子在抗蚀剂和基片中的散射引起图形的改变，它严重地影响了图形的分辨率。有多种方法对邻近效应进行修正和剂量调整、图形调整等。我们以ＪＢＸ－５０００ＬＳ为手段，用三种方法：１．图形尺寸修正，１２大小图分类和剂量分配，３图形分层和大小电流混合曝光，对邻近效应进行了修正，均取得较好效果。     

OMR-85光刻胶的研究与应用

在半导体制造中，光刻胶是重要的原材料之一，本文从转速与膜厚，感光灵敏度，图形变化差等方面对ORM-85光刻胶进行了研究，得出了用于大生产的一套工艺，解决了接触式曝光方式粘版的问题及提高了产能。     

电子束直接曝光机简介

电子束直接曝光机简介郑国强（甘肃平凉市电子部第４５研究所，７４４０００）１引言电子束曝光技术是集光、机、电、计算机和超高真空技术为一体的综合性技术，它可以把亚微米工艺的集成电路和器件图形直接光刻在Ｓｉ和ＧａＡｓ等圆片上。电子束直接曝光设备在军事微电子...     

ZEP520正性电子抗蚀剂的工艺研究

详细研究了ZEP520在Si衬底上的对比度、灵敏度、分辨率，并分析了曝光剂量、抗蚀剂厚度对ZEP520线条和圆孔尺寸的影响；同时还初步研究了ZEP520在GaAs衬底上的曝光工艺。实验结果表明，ZEP520的灵敏度远高于PMMA，在Si和GaAs上用ZEP520能分别制作出100nm和130nm宽的细线条，通过预烘GaAs衬底，可以消除ZEP520中的裂纹，因此用ZEP520制作器件或电路中各种细小凹槽图形是十分有利的。     

电子束光刻的快速邻近效应校正

提出了实现电子束光刻的快速邻近效应校正的分级模型.首先利用矩阵实现内部最大矩形和顶点矩形的快速替换,然后对内部最大矩形和顶点矩形进行校正迭代.在校正迭代的过程中,用局部曝光窗口与曝光强度分布函数直接卷积计算邻近图形对关键点产生的有效曝光剂量,将整个曝光块近似为一个大像点,以计算全局曝光窗口中的曝光图形对关键点产生的有效曝光剂量,实现了快速图形尺寸校正.在与同类软件精度相同的情况下,提高了运算速度.     

一种提高无掩膜光刻机图形质量的方法

针对无掩膜光刻技术在进行大面积图形曝光时会出现曝光质量差,精度低,程序繁等问题,该文提出了一种改善无掩膜光刻机图形质量的方法。通过设置“L”型定位标记将图形尺寸进行精确定位,再通过单场图像格式重命名系统,解决大面积图形切割过程中的乱序问题,最后提出了一种寻找最佳曝光位置的方法,以提高单场图形的曝光质量。该文提出了一种减小大面积图形拼接误差的方法,以提高整体图形的拼接质量;同时还提出了一种二次光刻的对准方法及对准误差校正方法,该方法与已有的套刻方法有区别。通过实验进行验证和分析,结果表明,该方法能有效地提高大面积图形的曝光质量,x、y方向的拼接误差距离均缩小到1 μm内,对准误差精度达到±0.3 μm。该研究为后续的光刻工艺及湿法腐蚀工艺奠定了理论基础。     

Scanning probe microscope analysis of microstructures in optically variable devices

The fine-scale features of optically variable devices (OVDs) fabricated in resist by electron beam lithography have been examined using scanning probe microscopy (SPM). These features have included patterns of gratings, micro-text and geometrical images. Scanning probe microscopy has provided information on the groove angle, depth of profile and spatial frequency of the features as determined by the details of processing of the image. The OVD patterns formed in EBR-9 and X-AR-P 7400 resists exhibited a more rounded profile with a lower side-wall angle than in ZEP-7000 and PMMA resists.     

Fabrication of carbon nanotube arrays for field emission and sensor devices by nanoimprint lithography

This work brings forth the idea of incorporating insulation in the resist used for ultraviolet (UV) curing nanoimprint lithography (NIL). Carbon nanotubes (CNTs) are grown in the space between two insulated resist patterns on the conductive substrate to make CNTs arrays. Two imprinting processes, soft UV curing NIL with DRPPR process and novel NIL without cured residual resist, are presented to achieve the insulation patterns. First the fabricating process is performed using a polydimethylsiloxane (PDMS) stamp. Subsequently, inductively coupled plasma (ICP) is essential to wipe off the residual resist film. To avoid the ICP process, a novel UV curing NIL is presented. Its special hard quartz stamp with chrome shelter can protect the residual resist film out of curing during the UV exposure process, and the uncured resist can be easily removed by ultrasonic vibration in organic solutions. The CNT arrays are prepared on the patterned substrates by the pyrolysis of iron phthalocyanine (FePc). Field emission experiments reveal that the turn-on field of those CNTs arrays is low to 1.3 V/um.     

光刻中驻波效应的影响分析

驻波效应是抗蚀剂在曝光过程中的寄生现象。一般认为,驻波效应对薄胶的光刻图形有较大的影响,而对厚胶的光刻图形影响不大。根据DILL曝光模型进行了模拟计算,分析了在曝光过程中抗蚀剂折射率的改变对驻波强度和位置的影响以及驻波效应引起抗蚀剂曝光剂量分布的变化,并结合MACK显影模型分析了当抗蚀剂的厚度改变时,驻波效应对其显影轮廓的影响程度,计算分析得出了一个可以不采用后烘工序的抗蚀剂厚度值。     

用于T形栅光刻的新型移相掩模技术

根据移相掩模基本原理,通过光刻工艺模拟提出了一种适于T形栅光刻的新型移相掩模技术——M-PEL。初步实验证明,M-PEL技术可在单层厚胶上经一次光刻形成理想的T形栅抗蚀剂形貌。     

Fabrication of hp 32 nm resist patterns using near-field lithography

Near-field lithography (NFL) has no fundamental limit such as the diffraction limit of light. However, in order to fabricate resist patterns with hp 32 nm, thorough optimization of various processes are indispensable. Previously, we reported on the use of fine and ultra-thin top-layer resist, and designs and fabrication of our special masks. In this paper, the effect of the total resist thickness on the near-field distribution is analyzed by the finite-difference time domain analyses and compared with our experiments. For the fabrication of hp 32 nm patterns, the total resist thickness as well as the tri-layer resist process are accordingly optimized. By the near-field exposure using an i-line mercury lamp and the dry-etching process for thin top-layer photo-resist, we have successfully fabricated the hp 32 nm resist pattern of 120 nm height.     

Novel approach to simulation of the silylation bake in the DESIRE process

This contribution presents a simple quantitative model — the reaction dominated propagation model — for the simulation of the silylation bake in the DESIRE process. This allows to do very effectively simulation of three dimensional silylated resist patterns. The model is discussed and resist calibration is demonstrated for the i-line resist PLASMASK 206-I from JSR-Electronics     

Distortion reduction by load release for imprint lithography

Due to the light source limitation and prohibitive cost inherent in conventional photolithography, various nontraditional patterning technologies, such as imprint lithography, electron beam or X-ray lithography have been attempted over the past 10 years. In this paper, a UV imprint lithography process is introduced for patterning sub-micrometer structures by using a soft PDMS mould, and an imprint experimental device with a loading mechanism driven by PZT for generating a time-variant load is described. As shown experimentally, an increased pressing load will reduce the thickness of the resist layer, leading to a reliable etching-through of the resist. It is found, however, that the mechanical pressing can generate geometrical distortion on the patterned resist mainly due to the elasticity. Incorporated with the use of a low viscosity photo-curable resist, a loading process with a load release step is proposed to reduce the geometrical distortion on the resist patterns. In the loading process, the loading force is partially released after the press peak but before the resist curing. Such a loading process can reduce the elastic distortion while attaining a thin remained resist layer. It is shown that this loading process, called Distortion Reduction by Load Release or DRLR simply can be combined with an imprint process for different patterning areas and feature sizes.     

Electron beam lithography at 10 keV using an epoxy based high resolution negative resist

The behaviour of a new epoxy based resist (mr-EBL 6000.1 XP) as a negative resist for e-beam lithography is presented. We demonstrate that it is possible to define sub-100 nm patterns when irradiating thin (120 nm) layers of resist with a 10 keV electron beam. The dependence of resolution and remaining thickness on electron dose, electron energy and photo acid generator (PAG) content is determined. After the electron beam lithography process, the resist is used as a mask for reactive ion etching. It presents a good etch resistance, that allows transfer of patterns to the substrate with resolution below 100 nm.     

A method to restrain the charging effect on an insulating substrate in high energy electron beam lithography

Pattern distortions caused by the charging effect should be reduced while using the electron beam lithography process on an insulating substrate. We have developed a novel process by using the SX AR-PC 5000/90.1solution as a spin-coated conductive layer, to help to fabricate nanoscale patterns of poly-methyl-methacrylate polymer resist on glass for phased array device application. This method can restrain the influence of the charging effect on the insulating substrate effectively. Experimental results show that the novel process can solve the problems of the distortion of resist patterns and electron beam main field stitching error, thus ensuring the accuracy of the stitching and overlay of the electron beam lithography system. The main characteristic of the novel process is that it is compatible to the multi-layer semiconductor process inside a clean room, and is a green process, quite simple, fast, and low cost. It can also provide a broad scope in the device development on insulating the substrate,such as high density biochips, flexible electronics and liquid crystal display screens.