一种低电压低功耗Class-AB运算跨导放大器

提出了一种新型Class-AB全差分运算跨导放大器(OTA).该OTA基于一种结构简单的电压缓冲器,在大信号非线性工作时,能够输出不受静态偏置电流限制的瞬态电流,提高了摆率和建立速度;同时,该结构还能够增强直流增益、增益带宽积等小信号特性,适合于低功耗开关电容电路的应用.另外,该OTA结构简单,适合于低电压工作.采用0.18μm CMOS工艺进行仿真,结果表明,该OTA结构能够在1V电源电压下工作.     

一种低电压CMOS折叠-共源共栅跨导运算放大器的设计

设计了一种全差分折叠-共源共栅跨导运算放大器,并将其应用于80 MHz开关电容带通Δ-Σ A/D转换器中.该跨导运算放大器采用0.35 μm CMOS N阱工艺实现,工作于2.5 V电源电压.模拟结果表明,该电路的动态范围为80 dB、直流增益63.4 dB、单位增益带宽424 MHz;在最大输出摆幅、建立精度为0.1%时,建立时间为7.5 ns,而功耗仅为7.5 mW.     

一种高增益高电流效率的运算跨导放大器

为了提高增益自举OTA的电流效率,对主运放、辅助运放及其共模反馈电路进行了电流复用,在华宏0.35μm工艺5 V电源电压下实现了一种具有大DC增益(大于121 dB)、高电流效率(大于1 146 MHz*pF/mA)、宽差分输出动态范围(大于9 V)的OTA结构.     

低压Rail-to-Rail CMOS运算放大器的设计

基于0.5μm标准CMOS工艺,设计了一种带有恒跨导输入级的轨对轨(rail-to-rail)低压CMOS运算放大器.采用折叠式共源共栅差分电流镜放大器输入级和改进的CMOS AB类输出级,实现了电源满幅度的输入输出和恒输入跨导.用Cadence Spectre仿真器,对整个电路在3.3 V工作电压下进行仿真,其直流开环增益AV=70.6 dB,相位裕度PM=71°,单位增益带宽GB=1.37 MHz.芯片面积为0.7 mm×0.4 mm.实际测试结果与模拟结果基本一致.     

高性能CMOS运算放大器的设计

基于0.5μm标准CMOS工艺,利用折叠式共源共栅电路和简单放大器级联结构,设计了一种增益高、建立时间短、稳定性好和电源抑制比高的低压CMOS运算放大器.用Cadence Spectre对电路进行优化设计,整个电路在3.3V工作电压下进行仿真,其直流开环增益100.1dB,相位裕度59°,单位增益带宽10.1MHz,建立时间1.06μs.版图面积为410μm×360μm.测试结果验证了该运算放大器电路适用于电源管理芯片.     

CMOS浮地电源交叉耦合运算跨导放大器

提出了一种高线性度运算跨导放大器．该电路采用ＣＭＯＳ对管和浮地电源交叉耦合作输入级。对所描述的电路进行了理论分析和计算机模拟．结果表明，在传输特性的非线性误差不大于１％时，电路的差动输入电压范围可达±２．８Ｖ。     

用于高速高分辨率ADC的CMOS全差分运算放大器的设计

高性能全差分折叠式共源共栅型跨导运算放大器采用 12 位精度,60 MHz采样速率的模数转换器芯片,采用0.35μm CMOS工艺,工作在3.3 V电源电压下。电路模拟结果表明,基于其独特的增益倍增结构,该运算放大器直流增益达到94.4 dB,驱动2 pF负载时,相位裕度为62°,单位增益带宽达到260 MHz,电路功耗为27 mW。     

线性跨导运算放大器的改进设计

针对现有的线性跨导运算放大器存在的主要问题设计了一个新的线性ＯＴＡ，模拟结果表明在输入电压从－０．８Ｖ到＋０．８Ｖ变化时，其线性误差小于±１．５％。     

一种0.18μm CMOS低电压低功耗跨导运算放大器

采用TSMC 0.18μm CMOS工艺,设计了一种低电压、低功耗跨导运算放大器。基于BSIM3V3.1Spice模型,采用Hspice对整个电路进行仿真。在±0.75V电源电压下,电路的直流开环增益达到83dB,相位裕度为63°,功耗为14μW。采用一种应用于低电源电压、低功耗的基准电路,不仅可为运放提供稳定的偏置电流,而且进一步降低了电路的总体功耗。     

一种用于开关电容电路的高性能运算放大器

设计了一种高性能BCMOS全差分运算放大器.该运放采用复用型折叠式共源共栅结构、开关电容共模反馈以及增益增强技术,在相同功耗和负载电容条件下,与传统CM0S增益增强型运算放大器相比,具有高单位增益带宽、高摆率及相位裕度改善的特点.在Cadence环境下,基于Jazz 0.35μm BiCMOS标准工艺模型,对电路进行Spectre仿真.在5 V电源电压下,驱动6pF 负载时,获得开环增益为115.3 dB、单位增益带宽为161.7 MHz、开环相位裕度为77.3°、摆率为327.0 V/μm、直流功耗(电流)为1.5 mA.     

异步Sigma-Delta调制的系统级设计

异步sigma-delta调制(asynchronous sigma-delta modulator,ASDM)在30-MHz带宽VDSL线路驱动器应用中,输出缓冲器的传输延时限制了系统的性能。本文采用时域分析的方法,得到了1阶、2阶ASDM系统的振荡频率与输入信号之间的关系,并给出了系统增益的表达式和3次谐波计算的经验公式,经Matlab仿真验证,具有较高的精度。本文的工作对ASDM的其他应用也具有较好的指导作用。     

高阶级联多位∑-△调制器Simulink仿真设计

为了在低过采样率下实现大带宽、高精度的∑-△调制器,文中采用了级联2-1—1结构,前两级用一位量化器,在最后一级采用4位量化器。讨论了调制器中时钟抖动、热噪声、运放有限直流增益等非理想因素对调制器性能的影响。重点考虑最后一级反馈回路中多位DAC失配引起的非线性,并采用DWA算法对其进行线性化。在Simulink环境下对调制器做行为级仿真,包括理想与非理想模型。在16倍过采样率、35．2MHz采样频率下,可以达到90dB的信噪比。     

Cascade SD modulator for low-voltage wideband applications

A new cascade SigmaDelta modulator architecture with unity signal transfer function is presented which avoids the need for digital filtering in the error cancellation logic. The combination of these two aspects makes it highly tolerant to noise leakages, very robust to nonlinearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioural simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications.     

An integrated low-voltage class AB CMOS OTA

We present a new circuit topology for a low-voltage class AB amplifier. The circuit shows superior current efficiency in the use of the supply current to charge and discharge the output load. It uses negative feedback rather than component matching to optimize current efficiency and performance, resulting in a current boost ratio exactly equal to one. Measurement results for an example circuit fabricated in a 2-μm CMOS process are given. The circuit uses a quiescent supply current of 0.2 μA and is able to settle to a 1% error in 1.1 ms for a 0.4-V input step and a load capacitance of 35 pF. The circuit design is straightforward and modular, and the core circuit can be used to replace the differential pair of other op-amp topologies     

A low-voltage switched-current delta-sigma modulator

This paper presents the design of a fully differential switched-current delta-sigma modulator using a single 3.3-V power-supply voltage. At system level, we tailor the modulator structure considering the similarity and difference of switched-capacitor and switched-current realizations. At circuit level, we propose a new switched-current memory cell and integrator with improved common mode feedback, without which low power-supply-voltage operation would not be possible. The whole modulator was implemented in a 0.8-μm double-metal digital CMOS process. It occupies an active area of 0.53×0.48 mm² and consumes a current of 0.6 mA from a single 3.3-V power supply. The measured dynamic range is over 10 b     

三阶一位量化CIFB结构∑-△ADC调制器设计

提出了一种基于Maltab SIMULINK的Sigma-Delta调制器的设计与仿真方法,采用单环三阶CIFB结构、一位量化器位数和256倍过采样率,设计中对噪声传输函数的零极点和系统反馈系数进行了优化,缩小了模拟电路的设计难度,提升了系统稳定性.在考虑积分器的有限直流增益、饱和电压、压摆率和增益带宽等非理想因素情况下进行建模,得到了SNDR和ENOB分别为123 dB,20.14 bits,仿真结果表明,该结构可在低量化位数的情况下,得到较高的精度和较好的稳定性,可在高层次上指导调制器晶体管级电路设计.     

A Multistage Closed-loop Sigma-Delta modulator (MSCL)

A new family of high order Sigma Delta modulators called MSCL (Multi Stage Closed-loop) is presented in this paper. They use a global feedback to lower the sensitivity to circuit imperfections. This feedback from the output of the modulator is the sum of the output of each comparator so that no digital prefiltering is required before summing up these signals. However, easy calibration will be required to compensate for the feedback imperfections.MSCL modulators present the same insensitivity to circuit imperfections as classical multi-order one-bit converters, but reach the performance of high-order MASH (MultistAge noise SHaping) modulators. They help make high-order low-pass or band-pass modulators without limit cycles so that their quantizing noise characteristics are similar to those predicted by the linear simplified model.     

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

Enhancing output voltage swing in low-voltage micro-power OTA using self-cascode

It is shown how a self-cascode configuration can be profitably used in a micro-power operational transconductance amplifier (OTA), to enhance the output voltage swing, which eventually results in a power consumption reduction. A practical design example is proposed and used in order to discuss and quantify the circuit performance.