面向寄存器的流水线处理器建模及验证方法

提出了一种新的流水线处理器功能的验证方法,这种方法的主要思想是通过验证流水线处理器中所有寄存器的功能来验证处理器的功能.流水线处理器绝大部分是由同步电路组成的,同步电路的状态则完全由寄存器的状态决定,因此如果能够保证每个寄存器功能正确就可以保证整个同步电路功能正确.对于流水线处理器来说,寄存器状态的变迁是由处理器的原始输入和寄存器本身状态决定的.原始输入包括控制信号(如复位信号)和数据输入(如指令输入).如果把对每个寄存器的赋值操作转换成对控制信号和数据输入的操作,就可以生成一个验证序列,这个序列包括每个时钟周期控制信号和数据输入的值.有了这个序列就可以把目标设计和参考模型进行结果比较,从而验证目标设计功能是否正确.同时这种方法也便于调试.     

一种基于状态转换图的时序电路等价验证算法

提出一种基于状态转换图的时序电路等价验证算法。此算法通过验证两时序电路的状态转换图是否同构．得到两电路是否等价的信息。若两状态转换图同构，则两图中的状态可一一匹配为等价状态对，算法将状态转换图存储为待验证等价状态对的形式，若所有待验证等价状态对均为等价，则两时序电路等价，反之，则不等价。此算法对ISCAS89测试电路进行验证，与基于BDD方法的SIS系统和基于时间帧展开算法相比，均有较好的结果。     

基于低功耗的BIST测试生成结构优化设计

针对内建自测试(Built-In Self-Test,BIST)技术的伪随机测试生成具有测试时间过长,测试功耗过高的缺点,严重影响测试效率等问题,提出一种低功耗测试生成方案,该方案是基于线性反馈移位寄存器(LFSR)设计的一种低功耗测试序列生成结构--LP-TPG(Low Power Test Pattern Generator),由于CMOS电路的测试功耗主要由电路节点的翻转引起,所以对LFSR结构进行改进,在相邻向量间插入向量,这样在保证原序列随机特性的情况下,减少被测电路输入端的跳变,以ISCAS'8585基准电路作为验证对象,组合电路并发故障仿真工具fsim,可得到平均功耗和峰值功耗的降低,从而达到降低功耗的效果.验证结果表明,该设计在保证故障覆盖率的同时,有效地降低了测试功耗,缩短了测试序列的长度,具有一定的实用性.     

面向寄存器的流水线处理器建模及验证方法

提出了一种新的流水线处理器功能的验证方法 ,这种方法的主要思想是通过验证流水线处理器中所有寄存器的功能来验证处理器的功能 .流水线处理器绝大部分是由同步电路组成的 ,同步电路的状态则完全由寄存器的状态决定 ,因此如果能够保证每个寄存器功能正确就可以保证整个同步电路功能正确 .对于流水线处理器来说 ,寄存器状态的变迁是由处理器的原始输入和寄存器本身状态决定的 .原始输入包括控制信号 (如复位信号 )和数据输入 (如指令输入 ) .如果把对每个寄存器的赋值操作转换成对控制信号和数据输入的操作 ,就可以生成一个验证序列 ,这个序列包括每个     

时序电路的状态验证研究与设计

采用二元判定图(BDD)作为工具来描述时序电路是非常有意义和有效的.本文通过对BDD的简化达到对状态变换图(STG)输入、路径和状态的压缩,从而提高状态遍历的效率,另外根据电路的特点,提出状态冲突和不相交分解的启发技术以有效地完成验证.     

时序电路可及状态的枚举和自动测试生成

复杂时序电路的测试生成被公认为VL-SI电路测试的难题之一。本文在分析已发表文献对此问题研究情况的基础上,提出一种实用的、可靠的测试生成方法。本方法的特点有二。一是以时序电路可及状态的分析为依据,建立同步、异步时序电路测试的统一数学模型,完全地、准确地反映电路的稳态功能。二是以图论算法为工具,从电路强连通状态转换图中找出最优测试向量序列。此法适用于数字系统层次或功能测试,有效地降低计算复杂性,加快测试生成速度,可望发展成为VLSI电路实用化测试生成方法的一条新途径。     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现 ,提出具有信息恢复能力的静态绝热 CMOS记忆电路 .认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体 ,由主触发器集合和从触发器集合相互连接构成 ,其中含有输出和反馈从触发器 .采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离 .还设计出 5 4 2 1BCD码 10进制和 7进制可变计数器 (带有进位输出从触发器和反馈清 0从触发器 ) ,用计算机模拟程序检验电路的正确性     

低功耗单输入跳变测试理论的研究

介绍一种随机单输入跳变(RSIC)低功耗测试方案.基本原理是在原线性反馈移位寄存器(LFSR)的基础上加入代码转换电路,对LFSR输出的随机测试向量进行变换,从而得到随机单输入跳变测试序列,可以在不损失故障覆盖率的前提下,降低被测电路的开关翻转活动率,实现测试期间的低功耗.文中给出了RSIC测试序列的生成准则,以CC4028集成电路为被测电路作了研究,结果表明在进行低功耗测试时,单输入跳变测试序列比多输入跳变测试序列更加有效,在不影响故障覆盖率的情况下可以将开关翻转活动率降低到58%,证实了该方案的实用性.     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现,提出具有信息恢复能力的静态绝热CMOS记忆电路.认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体,由主触发器集合和从触发器集合相互连接构成,其中含有输出和反馈从触发器.采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离.还设计出5421BCD码10进制和7进制可变计数器(带有进位输出从触发器和反馈清0从触发器),用计算机模拟程序检验电路的正确性.     

静态绝热CMOS记忆电路和信息恢复能力

通过等效电路分析、考虑参数选取和整体时序电路的实现,提出具有信息恢复能力的静态绝热CMOS记忆电路.认为整体绝热电路结构最好融合输入、输出电路和记忆电路、时序电路为一体,由主触发器集合和从触发器集合相互连接构成,其中含有输出和反馈从触发器.采用绝热取样输入电路实现信息记忆单元接收代码和保存信息时将信息单元与外输入隔离.还设计出5421BCD码10进制和7进制可变计数器(带有进位输出从触发器和反馈清0从触发器),用计算机模拟程序检验电路的正确性.     

一类基于时变逻辑的序列发生器

基于带记忆组合逻辑的序列发生器虽然抗传统的相关攻击,但易受线性时序电路逼近攻击.结合表更新的思想,本文给出了一类基于时变逻辑的序列发生器模型,并分析了输入输出间的相关性等密码学性质.许多密码体制都可归于此种模型,该模型对设计序列发生器有借鉴意义.     

通用稳态电路分析平台的设计

电路计算中通常需要进行大量的矩阵计算。现已广泛使用计算机对电路进行辅助分析和设计。平台采用具有通用性的列表法,利用Matlab的强大的计算功能和它的GUI界面开发的功能,实现了对稳态电路的自动求解。用户不需要编程,只需输入电路的相关信息,便可直接计算出电路中的各个结点电压、支路电压、支路电流,并且画出各种所需波形图。平台为稳态电路的分析提供了有效的辅助工具,特别是能应用在模拟电路的教学中。     

Robust tests for parity trees

Linear logic circuits are used extensively in digital computing and signal processing systems. They are constructed as regular arrays (for example as cascade or tree circuits), employing linear gates such as Exclusive OR (EOR) and Exclusive NOR (ENOR) gates. Earlier studies on fault diagnosis in linear logic circuits were based on the classical fault model of line stuck-at faults. Transistor stuck-open (SOP) and stuck-on (SON) faults in linear circuits were studied recently, but the effect of signal transients due to circuit delays and time skews in input changes were not considered in the derivation of test sequences. These latter factors are known to cause invalidation of two pattern tests for stuck-open faults. In this article we consider the problem of generating robust tests for linear logic circuits. These tests are not affected by circuit transients caused by delays. A major finding in this paper is that, if the test invalidation problem is redressed by introducing robust tests, the test length becomes a linear function of the depth of the circuit as opposed to the constant number of tests derived in previous studies, by neglecting circuit transients. A lower bound on minimum number of distinct test patterns needed for a tree of EOR gates of depthd is derived. This number depends on the specific implementation of the gate. Robust test-generation procedures are proposed for both single and multiple fault models and their optimalities are argued. Given that every gate in a parity tree is robustly testable, a test sequence that can test for all faults in the circuit, regardless of the nature of gate implementation, is calleduniversal robust test sequence for a parity tree. Finally we propose an optimal universal robust test sequence.     

Switching activity estimation of VLSI circuits using Bayesian networks

Switching activity estimation is an important aspect of power estimation at circuit level. Switching activity in a node is temporally correlated with its previous value and is spatially correlated with other nodes in the circuit. It is important to capture the effects of such correlations while estimating the switching activity of a circuit. In this paper, we propose a new switching probability model for combinational circuits that uses a logic-induced directed-acyclic graph (LIDAG) and prove that such a graph corresponds to a Bayesian network (BN), which is guaranteed to map all the dependencies inherent in the circuit. BNs can be used to effectively model complex conditional dependencies over a set of random variables. The BN inference schemes serve as a computational mechanism that transforms the LIDAG into a junction tree of cliques to allow for probability propagation by local message passing. The proposed approach is accurate and fast. Switching activity estimation of ISCAS and MCNC circuits with random and biased input streams yield high accuracy (average mean error=0.002) and low computational time (average elapsed time including CPU, memory access and I/O time for the benchmark circuits=3.93 s).     

一种基于二叉树的测控设备故障诊断方法

针对传统故障树知识规则存储和诊断推理算法不易实现的问题,提出了一种基于二叉树的故障诊断方法。首先,通过对故障树与二叉树转换规则与方法的分析,直接构建出测控设备故障二叉树集;然后,利用二叉树节点左右编码值来定位该节点的方法,建立故障诊断规则库;最后,采用遍历诊断规则库的搜索算法实现对故障定位。在测控设备中的应用表明,该方法能够方便地建立诊断规则库,准确定位设备故障,可有效提高设备故障诊断效率。     

A partitioning technique for reducing the computational complexity of probabilistic fault detection in general combinational circuits

This paper examines the impacts of different types of circuit partitioning on reducing the computational complexity for computing the fault detection probability, which usually grows exponentially with the number of input lines in the given circuit. Partitioning a large combinational circuit into arbitrary subcircuits does not, in general, reduce the computational time complexity of the fault detection probability. In fact, partitioning a given circuit into general subcircuits is expected to increase the time complexity by the amount of time spent in the partition process itself. Nevertheless, it will be shown that decomposing a general combinational circuit into its modules (supergates) such that these modules constitute the basic elements of a tree circuit (network) considerably reduces the computational complexity of the fault detection probability problem. Toward this goal, two algorithms are developed. The first partitions a given circuit into maximal supergates whenever this is possible. Its computational complexity depends linearly on the number of edges (or lines) and nodes (or gates) of the circuit. The second computes the exact detection probabilities of single faults in the tree network and its computational complexity grows exponentially with the largest number of input lines in any of the network maximal supergates rather than the total number of inputs. The case of multi-output circuits is also discussed.     

Synchronizing sequences and symbolic traversal techniques in test generation

Asynchronizing sequence drives a circuit from an arbitrary power-up state into a unique state. Test generation on a circuit without a reset state can be much simplified if the circuit has a synchronizing sequence. In this article, a framework and algorithms for test generation based on themultiple observation time strategy are developed by taking advantage of synchronizing sequences. Though it has been shown that the multiple observation time strategy can provide a higher fault coverage than the conventional single observation time strategy, until now the multiple observation time strategy has required a very complex tester operation model (referred asMultiple Observation time-Multiple Reference strategy (MOMR) in the sequel) over the conventional tester operation model. The overhead of MOMR, exponential in the worst case, has prevented widespread use of the method. However, when a circuit is synchronizable, test generation can employ the multiple observation time strategy and provide better fault coverages, without resorting to MOMR. This testing strategy is referred asMultiple Observation time-Single Reference strategy (MOSR). We prove in this article that the same fault coverage, that could be achieved in MOMR, can be obtained in MOSR, if the circuit under test generation is synchronizable. We investigate how a synchronizing sequences simplifies test generation and allows to use MOSR under multiple observation time strategy. The experimental results show that higher fault coverages and large savings in CPU time can be achieved by the proposed framework and algorithms over both existing single observation time strategy methods as well as other multiple observation time strategy methods.     

核电站继电保护控制电路卡的检测和维修技术

介绍了一种新型继电保护控制卡件(以下简称卡件)的检测技术--老化状态检测法:通过对电路图原理分析,确定各个电路节点的基准工作电压(设计电压)、维持正常工作的极限工作电压(上、下限),以及状态转换的时间,再根据具体的电路卡件来设计一个状态检测装置,对卡件进行非破坏性的检测和试验,即可知道被检测的卡件是否还能正常工作;如果检测时输入卡件的序列号,形成每个卡件专有的历史性能数据,就可根据各个节点的电压或者状态转换时间的趋势变化,评估卡件上某些元器件的老化状态,这样就可以在卡件失效前发现问题,避免卡件故障影响核电站的正常运行;对卡件进行恢复性维修,延长卡件的寿命。通过对LG_A325E过流保护卡件和LG_A326E过负荷保护卡件的检测和维修,取得了预期的检测结果,并意外地发现了卡件设计上的缺陷,提出相应的解决措施。     

Variations on a theme by Huffman

In honor of the twenty-fifth anniversary of Huffman coding, four new results about Huffman codes are presented. The first result shows that a binary prefix condition code is a Huffman code iff the intermediate and terminal nodes in the code tree can be listed by nonincreasing probability so that each node in the list is adjacent to its sibling. The second result upper bounds the redundancy (expected length minus entropy) of a binary Huffman code byP_{1}+ log_{2}[2(log_{2}e)/e]=P_{1}+0.086, whereP_{1}is the probability of the most likely source letter. The third result shows that one can always leave a codeword of length two unused and still have a redundancy of at most one. The fourth result is a simple algorithm for adapting a Huffman code to slowly varying esthnates of the source probabilities. In essence, one maintains a running count of uses of each node in the code tree and lists the nodes in order of these counts. Whenever the occurrence of a message increases a node count above the count of the next node in the list, the nodes, with their attached subtrees, are interchanged.     

基于交织的二元及四元完备序列和序列偶的构造方法

基于交织技术,提出了三类二元及四元完备序列和序列偶的构造方法。分别利用二元完备序列、二元完备互补序列对和二元完备序列偶作为初始序列,通过合理设计带符号移位序列,基于交织获得了不同的二元及四元完备序列和序列偶。这些构造方法均可不断递归地进行,从而获得更多具有新参数的完备序列及完备序列偶。该方法通过引入带符号的移位序列,在一定程度上改善了目标序列的相关性能,为序列的构造提供了新的思路。