Novel through-silicon vias for enhanced signal integrity in 3D integrated systems

In this paper, a new type of through-silicon via (TSV) for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types: bare signal TSVs and bare ground TSVs. First, by solving Poisson''s equation for cylindrical P-N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design, routing and placement can be retained after the application of the bare TSVs.     

Experimental characterization of coaxial through silicon vias for 3D integration

Coaxial through silicon via (TSV) technology is gaining considerable interest as a 3D packaging solution due to its superior performance compared to the current existing TSV technology. By confining signal propagation within the coaxial TSV shield, signal attenuation from the lossy silicon substrate is eliminated, and unintentional signal coupling is avoided. In this paper, we propose and demonstrate a coaxial TSV 3D fabrication process. Next, the fabricated coaxial TSVs are characterized using s-parameters for high frequency analysis. The s-parameter data indicates the coaxial TSVs confine electromagnetic propagation by extracting the inductance and capacitance of the device. Lastly, we demonstrate the coaxial TSVs reduce signal attenuation and time delay by 35% and 25% respectively compared to the shield-less standard TSV technology. In addition, the coaxial interconnect significantly decreases electromagnetic coupling compared to traditional TSV architectures. The improved signal attenuation and high isolation of the coaxial TSV make it an excellent option for 3D packaging applications expanding into the millimeter wave regime.     

RF-TSV design, modeling and application for 3D multi-core computer systems

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.     

Dynamic Self‐Repair Architectures for Defective Through‐silicon Vias

Three‐dimensional integration technology results in area savings, platform power savings, and an increase in performance. Through‐silicon via (TSV) assembly and manufacturing processes can potentially introduce defects. This may result in increases in manufacturing and test costs and will cause a yield problem. To improve the yield, spare TSVs can be included to repair defective TSVs. This paper proposes a new built‐in self‐test feature to identify defective TSV channels. For defective TSVs, this paper also introduces dynamic self‐repair architectures using code‐based and hardware‐mapping based repair.     

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.     

Repair the faulty TSVs with the improved FNS-CAC codec

Through-silicon via (TSV) is a key enabling technology for the emerging 3-dimension (3D) integrated circuits (ICs). However, the crosstalk between the neighboring TSVs is one of the important sources of the soft faults. To suppress the crosstalk, the Fibonacci-numeral-system-based crosstalk avoidance code ( FNS-CAC) is an effective scheme. Meanwhile, the self-repair schemes are often used to deal with the hard faults, but the repaired results may change the mapping between signals to TSVs, thus may reduce the crosstalk suppression ability of FNS-CAC. A TSV self-repair technique with an improved FNS-CAC codec is proposed in this work. The codec is designed based on the improved Fibonacci numeral system (FNS) adders, which are adaptive to the health states of TSVs. The proposed self-repair technique is able to suppress the crosstalk and repair the faulty TSVs simultaneously. The simulation and analysis results show that the proposed scheme keeps the crosstalk suppression ability of the original FNS-CAC, and it has higher reparability than the local self-repair schemes, such as the signal-switching-based and the signal-shifting-based counterparts.     

Fast algorithms for test optimization of core based 3D SoC

The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and power management issues. Also, the test procedure demands substantially more power than what is required in the normal functional mode, and hence, stringent thermal constraints during test need to be fulfilled to safeguard future performance and reliability of the chip. Since the overall 3D infrastructure depends on routing layer assignments, core allocation, and the geometry of TSV locations, these parameters should be given due consideration while designing the test-access-mechanism (TAM) that aims for minimizing overall test time satisfying power and TSV constraints. In this paper, we present a three-stage algorithm for reducing the test time in automated post-bond core-based 3D-SoCs, under a set of given constraints on test power, TAM-width, and the number of available TSVs. The proposed algorithm, when run on several ITC-02 SoC benchmarks, outperforms the algorithms presented in earlier work with respect to CPU-time, and additionally, reduces test time in many instances.     

2TF:一种协同考虑过硅通孔和热量的三维芯片布图规划算法

 三维芯片由多个平面器件层垂直堆叠而成,并通过过硅通孔(TSV,Through Silicon Via)进行层间互连,显著缩短了互连线长度、提高了芯片集成度.但三维芯片也带来了一系列问题,其中单个过硅通孔在目前的工艺尺寸下占据相对较大的芯片面积,且其相对滞后的对准技术亦降低了芯片良率,因此在三维芯片中引入过多的过硅通孔将增加芯片的制造和测试成本.垂直堆叠在使得芯片集成度急剧提高的同时也使得芯片的功耗密度在相同的面积上成倍增长,由此导致芯片发热量成倍增长.针对上述问题,本文提出了一种协同考虑过硅通孔和热量的三维芯片布图规划算法2TF,协同考虑了器件功耗、互连线功耗和过硅通孔数目.在MCNC标准电路上的实验结果表明,本文算法过硅通孔数目和芯片的峰值温度都有较大的降低.     

Scaling trends of power noise in 3-D ICs

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.     

面向三维集成封装的硅通孔电特性分析

主要针对三维集成封装中的关键技术之一的硅通孔互连技术进行电性能研究。首先简要介绍了硅通孔互连技术的背景,利用三维全波电磁仿真软件建立地．信号一地TSV模型,对其TDR阻抗和时域TDR／TDT信号进行分析,同时仿真分析了TSV互连线及介质基板所使用的材料和TSV半径、高度、绝缘层厚度等物理尺寸对三维封装中TSV信号传输性能的影响。研究结果可为工程设计提供有力的技术参考,有效地用于改善互连网络的S21,提高三维集成电路系统的性能。     

Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects

Pre-bond TSV testing and defect identification is important for yield assurance of 3D stacked devices. Building on a recently proposed pre-bond TSV probing procedure, this paper develops a three-stage optimization method named “SOS3” to greatly reduce TSV test time without losing the capability of identifying given number of faulty TSVs. The optimization stages are as follows. First, an integer linear programming (ILP) model generates a near-optimal set of test sessions for pre-bond defective TSV diagnosis. Second, an iterative greedy procedure sequences the application of those test sessions for quicker diagnosis. Third, a TSV defect identification algorithm terminates testing as quickly as possible, often before all sessions are applied. Extensive simulation experiments are done for various TSV networks and the results show that the SOS3 framework greatly speeds up the pre-bond TSV test.     

Fabrication and stress analysis of annular-trench-isolated TSV

The large mismatches among the coefficients of thermal expansion (CTE) of the metal via, insulator liner, and Si substrate of the through-silicon via (TSV) induce thermal stresses within and around the TSV during thermal-cycled fabrication processes. Reduction of thermal stress in the Si substrate is important for minimizing the deviations in the device characteristics. An annular-trench-isolated (ATI) structure was proposed for the TSV to solve the thermal issues, which occur during the three-dimensional (3D) integrated circuit (IC) integration, by stress redistribution. The concept of ATI TSV is based on retaining a Si-ring between the metal core and insulator layer during the fabrication process. We realized the ATI TSV using a via-last fabrication approach, with two deep silicon etching processes (Bosch processes) for the insulator layer and the metal core. Parylene-HT was utilized as the insulator to achieve high uniformity. With a vacuum-assisted filling system, the vias were filled with a solder material. ATI TSVs with diameters of 10 μm and 2-μm-thick Parylene-HT insulation layers were demonstrated. Studies on the thermal stress levels of the ATI TSV were carried out by finite-element method (FEM) simulation, along with comparisons with regular and annular TSVs. We revealed that the ATI TSV shows lower thermal stresses in the Si substrate than the regular and annular TSVs. The ATI TSV is a possible candidate for 3D IC integration with stress-sensitive devices.     

Architectural Implications and Process Development of 3-D VLSI$Z$-Axis Interconnects Using Through Silicon Vias

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance–capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense$Z$-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.     

X-ray inspection of TSV defects with self-organizing map network and Otsu algorithm

Through-silicon via (TSV) is one of the most critical elements in 3D integration, where defects such as unfilled bottom and holes are very common. Thus, defect detection is of great importance to improve products quality. In this work, a non-destructive TSV defect detection method using X-ray imaging is introduced. Seven features representative of TSVs are extracted from the images, and then inputted into a self-organizing map (SOM) network for classification and testing. The results demonstrate that the normal TSVs and defective TSVs can be distinguished obviously by SOM network. The voids inside the TSVs are further located qualitatively using the Otsu algorithm and verified by the SEM images. These prove the feasibility of X-ray inspection of TSV defects with SOM network and Otsu algorithm.     

基于TSV绑定的三维芯片测试优化策略

本文提出一种三维片上系统(3D SoC)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D SoC绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures

Through-silicon vias (TSVs) are critical components in most 3D architectures. In this paper, fully filled cylindrical Cu TSVs with a diameter of 5 μm and a depth of 25 μm were used to demonstrate quantitative assessment of the fabrication process and the interfacial adhesion of the TSVs. For TSV fabrication, the coverage of barrier and seed layers was respectively examined through dilute HF dipping and copper decoration plating. The adhesion between the TSVs and the substrate, which is of great importance for the functionality and long-term reliability of the TSVs, was characterized by four-point bending in combination with fractographic analysis. The scanning electron microscopic (SEM) images of the fracture indicate that the top of a TSV has better adhesion than the rest. This can be due to the non-uniformity of sidewall roughness and barrier thickness. A degradation of adhesion at the top was observed after thermal cycling tests, which seems to confirm the hypothesis of the influence of the roughness. These reliability tests should be taken as additional criteria for the assessment of TSV properties.     

Invited: Routing Strategies for Capacity-Efficient and Fast-Restorable Mesh Optical Networks

Wavelength division multiplexed (WDM)-based mesh network infrastructures that route optical connections using intelligent optical cross-connects (OXCs) are emerging as the technology of choice to implement the next generation core optical networks. In these architectures a single OXC is capable of switching tens of terabits of traffic per second. With such data transfer rates at stake, it becomes increasingly challenging for carriers to (1) efficiently and cost-effectively operate and manage their infrastructure, and (2) cope with network failures while guaranteeing prescribed service level agreements (SLAs) to their customers. Proper routing of primary and backup paths is a critical component of the routing and restoration architecture required to meeting these challenges. In this paper we review some of the various strategies and approaches proposed so far to intelligently route connections while at the same time providing guaranteed protection against various types of network failures. We explore the tradeoffs associated with these approaches, and investigate in particular different, sometimes competing aspects, such as cost/capacity required, level of protection (link vs. node failure), restoration time, and complexity of route computation.     

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 μm wide and 15 μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.