Transition Skew Coding for Global On-Chip Interconnect

This paper presents new simulation results of the previously proposed transition skew coding (TSC) for global on-chip interconnects. Considering 2-GHz global clock frequency at the 90-nm node, we show that TSC can be applied to broad range of wire length on both semiglobal and global metal layers, while maintaining its energy efficiency and its advantages in terms of crosstalk reduction and signal integrity, and wiring and repeater area minimization.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法.该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点,将它们混合插入到连线的合适位置,从而降低互连的延时和功耗.模拟结果表明,该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies

The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) and optics-based interconnects exhibit promising physical properties for replacing the current Cu/low-k-based global interconnects. We quantify the performance of these novel interconnects and compare them with Cu/low-k wires for future high-performance integrated circuits. The foregoing trends are studied with technology node and bandwidth density in terms of latency and power dissipation. Optical wires have the lowest latency and power consumption, whereas a CNT bundle has a lower latency than Cu. The new circuit scheme, i.e., “capacitively driven low-swing interconnect (CDLSI),” has the potential to effect a significant energy saving and latency reduction. We present an accurate analytical optimization model for the CDLSI wire scheme. In addition, we quantify and compare the delay and energy expenditure for not only the different interconnect circuit schemes but also the various future technologies, such as Cu, CNT, and optics. We find that the CDLSI circuit scheme outperforms the conventional interconnects in latency and energy per bit for a lower bandwidth requirement, whereas these advantages degrade for higher bandwidth requirements. Finally, we explore the impact of the CNT bundle and the CDLSI on a via blockage factor. The CNT shows a significant reduction in via blockage, whereas the CDLSI does not help to alleviate it, although the CDLSI results in a reduced number of repeaters due to the differential signaling scheme.      

一种高速片上互连接收电路设计

在片上通信领域,随着片上系统(SOC)以及片上网络(NOC)的发展以及集成核数的增加,全局互连成为片上设计性能与功耗瓶颈.低摆幅互连是一种兼顾高传输率和低能耗设计,它主要由发送电路和接收电路两部分构成.本文提出一种基于TSMC 90nm工艺的接收电路,适用于低摆幅的全局互连.该接收电路结构包括一种改进的灵敏放大器和模拟型判决反馈均衡器,用于消除传输线造成的码间串扰.电路在双时钟沿工作,传输率提升一倍.所设计的接收电路与相关结构相比,性能与单位能耗相当,但平均功耗有较大优势.     

全硅片上光互连用波导

较详细地分析了用于全硅片上光互连所用光波导（如多晶Si／SiO2、Si／SiO2、Si3N4/SiO2）需满足的基本条件、制作方法以及损耗机制,总结了目前的研究进展。     

On-Chip Optical Interconnect

We describe a cost-effective and low-power-consumption approach for on-chip optical interconnection. This approach includes an investigation into architectures, devices, and materials. We have proposed and fabricated a bonded structure of an Si-based optical layer on a large-scale integration (LSI) chip. The fabricated optical layer contains Si nanophotodiodes for optical detectors, which are coupled with SiON waveguides using surface-plasmon antennas. Optical signals were introduced to the optical layer and distributed to the Si nanophotodiodes. The output signals from the photodiodes were sent electrically to the transimpedance-amplifier circuitries in the LSI. The signals from the photodiodes triggered of the circuitries at 5 GHz. Since electrooptical modulators consume the most power in on-chip optical interconnect systems and require a large footprint, they are critical to establish on-chip optical interconnection. Two approaches are investigated: 1) an architecture using a fewer number of modulators and 2) high electrooptical coefficient materials.     

集成电路片内铜互连技术的发展

论述了铜互连取代铝互连的主要考虑,介绍了铜及其合金的淀积、铜图形化方法、以及铜与低介电常数材料的集成等。综述了ULSI片内铜互连技术的发展现状。     

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.      

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

In deep-submicron technologies, long interconnects play an ever-important role in determining the performance and reliability of core-based system-on-chips (SoCs). Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC, thereby allowing at-speed testing of interconnect crosstalk defects, while eliminating the need for test overhead and the possibility of over-testing. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.     

Jittery Signal Generation for High-Speed Interconnect Simulation

By generating clock and data waveforms in the frequency domain through a truncated Fourier series, absolute control over both voltage noise and symbol transition timing is achieved. A parameterized Fourier series signal model is derived and used to form clock and data waveforms exhibiting arbitrary noise and jitter characteristics. The method not only facilitates more accurate interconnect modeling in tools like Matlab and Simulink, but also provides a simple means for generating realistic signals that may be imported into Spice-based simulators.      

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses

This paper purposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing a dynamic relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like delayed data bus (DDB) and delayed clock bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB, respectively.      

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with $6sigma$ offset reliability at 5 Gb/s.      

Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces

Programmable logic cores (PLCs) offer a means of providing post-fabrication reconfigurability to a SoC design. This ability has the potential to significantly enhance the SoC design process by enabling post-silicon debugging, design error correction and post-fabrication feature enhancement. However, circuits implemented in general purpose programmable logic will inevitably have lower timing performance than fixed function circuits. This fundamental mismatch makes it difficult to use the PLC effectively. We address this problem by proposing changes to the structure of the PLC itself; these architectural enhancements enable circuit implementations with high performance interfaces. In previous work we addressed system bus interfaces, in this work we address direct synchronous interfaces. Our results show significant improvement in PLC interface timing, such that interaction with full-speed fixed-function SoC logic is possible. Our enhanced PLCs are able to implement direct synchronous interfaces running at, on average, 662 MHz (compared to 249 MHz in regular programmable logic). We are able to do this without compromising the basic structure or routiblity of the programmable fabric. At the same time, we show that the area overhead for these architectural changes was approximately 1%.      

高速低功耗多模分频器的设计

基于相位转换技术的多模分频器由于其在工作频率和功耗中能更好地折中而得到广泛的应用.为了进一步降低功耗,利用两级反相器对其相位信号进行整形,使工作频率最高的前两级÷2分频器能降低输出幅度的要求,从而大大降低功耗.这两级反相器还可以调整相位信号占空比为25%,甚至更小,从而增大相位控制信号的延时余量,实现无毛刺的加计数相位转换.基于相位转换4模分频器的基本原理,设计了一个2.55 GHz的多模分频器.仿真结果表明,采用0.35μm BiCMOS工艺,在3.3 V电源电压下,分频值为128～255,最大功耗不到14 mW.     

一款高速、低功耗的Sigma-Delta模数转换器

提出了一种高速、低功耗、高分辨率的新型Sigma-Delta模数转换器(ADC)结构。该结构选择过采样率(OSR)为32的4阶调制器设计以缓解输出速率和通带宽度的压力,采用级联和双量化的方法进行优化,并利用SIMSIDES工具(基于Simulink的Sigma-Delta仿真器)进行仿真。数字抽取滤波器部分由级联积分梳状(CIC)滤波器、有限长单位冲激响应(FIR)滤波器和半带(HB)滤波器组成,并且三级滤波器都采用了多相分解结构,以降低动态功耗。使用0.18μm的标准CMOS工艺实现数字抽取滤波器版图。仿真结果表明,在250 kHz带宽下,有效位宽(ENOB)为19 bit。     

新型高速低功耗动态比较器

基于预放大锁存理论,提出了一种新型高速低功耗动态比较器.该比较器采用预放大级、动态锁存器及输出缓冲级构成的三级结构,与传统比较器不同,该比较器采用了一种新型动态结构作为输出缓冲级以实现高速低功耗.在CSMC 0.5 μm/5 V Si CMOS工艺模型下,采用Hspice对电路进行模拟.结果表明在100 MHz的时钟下,精度可达0.2 mV,功耗仅为1.12 mw.     

Serial-Link Bus: A Low-Power On-Chip Bus Architecture

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus (PLB) architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus (SLB), transforms an n-bit conventional PLB into an n/m-line (serial link) bus. The advantage of SLBs is that they have fewer lines, and if the bus width is kept the same, SLBs will have a larger line pitch. Increasing the line width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m _opt and an optimum width to pitch ratio eta_opt exist, which minimizes the bus energy dissipation and maximizes the bus throughput per unit area. The optimum degree of multiplexing and optimum width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. Also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. HSPICE simulations show that for the same throughput per unit area as conventional parallel-line data buses, the SLB architecture reduces the energy dissipation by up to 31% for a 64-bit bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology.     

多层AHB系统中基于时分复用的高速从设备互连电路

片上系统在性能和功能上的突破性进展带来了新的挑战,包括大量IP模块之间的有效互连.虽然前人已经研究并实现了多种基于共享总线的多通道平行访问方案,但是当同一个IP块被多个通道同时访问时仍然存在数据传输的瓶颈.针对经常引起资源冲突的IP块,提出了一个基于时分复用的互连电路.该电路在同一个IP块被同时访问时重新安排传输信息,以时分复用的方式分配有限的资源.它将实现多个传输通道并行访问同一个IP核时不引入额外的延时,且对IP核是透明的.最后,在双层AHB总线系统的基础上实现了该电路.     

High-Speed and Low-Power GaAs Phase Frequency Comparator

A high-speed and low-power consumption phase frequency comparator (PFC) for a phase lock stable oscillator was designed and fabricated with a GaAs MESFET BFL circuit for the first time. The threshold voltage, gate width, and gate length of GaAs MESFET's in the PFC were determined by circuit simulations for a high-speed and low-power operation. The fabrication process used buried p-layer SAINT-FET's with 0.5-µm gate length. The fabricated PFC performed stable phase and frequency comparison up to 600 MHz at only 60 mW. Using dislocation-free wafers, the fabrication yield in the laboratory was more than 90 percent.