Shallow and deep dry etching of silicon using ICP cryogenic reactive ion etching process

We achieved to etch nanostructures as well as structures with high aspect ratios in silicon using an inductively coupled plasma cryogenic deep reactive ion etching process. We etched cantilevers, submicron diameter pillars, membranes and deep structures in silicon with etch rates between 13 nm/min and 4 μm/min. These structures find applications as templates for metal organic vapour phase epitaxial growth of GaN-based nanostructures for optoelectronic devices or they are the basic constituents of a nanoparticle balance in the subnanogram range and of a thermoelectric generator.     

Strategies in deep wet etching of Pyrex glass

This paper establishes the strategies for deep wet etching of one of the most common glasses: Pyrex. There are two way for increasing the etch depth: increasing the etch rate or increasing the resistance of the mask in the etching solution. The paper analyzes the methods for increasing the glass etch rate in HF solutions: annealing, concentration, ultrasonic agitation and temperature. The generation of the defects is investigated. The main factors that affect the degradation of the mask are: type, value and gradient of the residual stress and the hydrophilicity of the surface. Cr/Au mask is used for illustration. A new method for deep wet etching of glass using Cr/Au mask and photoresist is established. The result of this method is the best thus far as reported in the literature: 85 min deep wet etching in HF 49% which is equivalent to etching of more than 500 μm deep in the Pyrex glass material.     

Single mask fabrication process for movable MEMS devices

The current work reports on the realization of movable micromachining devices using self-aligned single-mask fabrication process. Only dry etching process utilizing inductively coupled plasma reactive ion etching was used to release 3D micro structures from single crystal silicon substrate. No wet etching process is required to release the structures as is the case with silicon on insulator (SOI) wafers. Also the developed process does not require an SOI substrate and accordingly dispensing with the application of a wet etching step, thus yielding uniform structures without stiction. The optimized process was applied to realize thermally actuated microgrippers. The article presents the development of the fabrication process and demonstrates the operation of the fabricated device. The optimized process provides an avenue for low cost fabrication of movable micromachining devices without the use of complicated wet etching steps typically associated with SOI substrates.     

Vertical mirrors fabricated by deep reactive ion etching forfiber-optic switching applications

We report on vertical mirrors fabricated by deep reactive ion etching of silicon. The mirror height is 75 μm, covering the fiber core of a single-mode fiber when the latter is placed into a groove of equal depth and etched simultaneously with the mirror. To obtain a uniform etch depth, etching is stopped on a buried oxide layer. Using the buried oxide as a sacrificial layer allows to fabricate mirrors with suspension and actuation structures as well as fiber-alignment grooves in one and the same processing step. A minimal mirror thickness of 2.3 μm was achieved, resulting in an aspect ratio higher than 30. The verticality was better than 89.3°. In the upper part of the mirror a surface roughness below 40 nm rms was obtained. At a wavelength of 1300 nm the reflectivity of the aluminum-coated mirrors was measured to be higher than 76%. Using a reactive ion etched mirror we have fabricated an optical fiber switch with electrostatic actuation. The coupling loss in the bar state of two packaged prototypes was between 0.6 and 1.7 dB and between 1.4 and 3.4 dB in the cross state. The switching time is below 0.2 ms     

Sacrificial wafer bonding for planarization after very deep etching

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by dry etching and anodic bonding combined with KOH etching are discussed. The polymer bonding has been applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridges     

Fabrication of buried microfluidic channels with observation windows using femtosecond laser photoablation and parylene-C coating

We developed an advanced method for fabricating microfluidic structures comprising channels and inputs/outputs buried within a silicon wafer based on single level lithography. We etched trenches into a silicon substrate, covered these trenches with parylene-C, and selectively opened their bottoms using femtosecond laser photoablation, forming channels and inputs/outputs by isotropic etching of silicon by xenon difluoride vapors. We subsequently sealed the channels with a second parylene-C layer. Unlike in previously published works, this entire process is conducted at ambient temperature to allow for integration with complementary metal oxide semiconductor devices for smart readout electronics. We also demonstrated a method of chip cryo-cleaving with parylene presence that allows for monitoring of the process development. We also created an observation window for in situ visualization inside the opaque silicon substrate by forming a hole in the parylene layer at the silicon backside and with local silicon removal by xenon difluoride vapor etching. We verified the microfluidic chip performance by forming a segmented flow of a fluorescein solution in an oil stream. This proposed technique provides opportunities for forming simple microfluidic systems with buried channels at ambient temperature.     

Focussed ion beam based fabrication of micro-electro-mechanical resonators

A simple and fast process to fabricate micro-electro-mechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented. The proposed process is realized on both 350 nm and 1.5 μm thin silicon-on-insulator (SOI) substrates, evaluating the possibilities for MEMS devices on thin SOI for future co-integration with CMOS circuitry on a single chip. Through the combination of conventional UV-lithography and focused ion beam (FIB) milling the process needs only two lithography steps, achieving ∼100 nm gaps, thus ensuring an effective transduction. Different FIB parameters and etching parameters and their effect on the process are reported.     

Photonic crystal slabs with hexagonal air holes fabricated by selective area metal organic vapor phase epitaxy

It is shown that the photonic crystal slab (PCS) with hexagonal air holes has band gaps in the guided mode spectrum, which can be compared to that of the PCS with circular air holes, thus it is also a good candidate to be used for the PC devices. The PC with hexagonal air holes and a = 0.5 μm and r = 0.15 μm was fabricated successfully by selective area metal organic vapor phase epitaxy (SA-MOVPE). The vertical and smooth sidewalls are formed and the uniformity is very good. The same process was also used to fabricate a hexagonal air hole array with the width of 0.1 μm successfully. The air-bridge PCS with hexagonal air holes and a = 0.3 μm and r = 0.09 μm was also fabricated successfully by SA-MOVPE. Further optimization of the growth conditions for the sacrificial layer and the selective etching of the GaAs cap layer is also needed. Our experimental results indicate that SA-MOVPE is a promising method for fabricating PC devices and photonic nanostructures.     

Vertical Mirror Fabrication Combining KOH Etch and DRIE of (110) Silicon

This paper presents fabrication of MEMS-actuated optical-quality vertical mirrors as the key active optical components in a silicon optical bench (SOB) technology. The fabrication process is based on a combination of potassium hydroxide (KOH) etch and deep reactive ion etching (DRIE) of (110) SOI wafers. The process starts by creating optical-quality vertical surfaces by KOH etch, followed by an oxidation step to protect them. The patterned wafer is then etched by DRIE to define actuators. The process is designed to allow the KOH etch and DRIE to be independently optimized without compromising either while at the same time meeting the challenge of lithography on high-aspect-ratio structures. Three variations of the fabrication process are demonstrated, two that use double masking layers and one that uses a silicon masking layer. We demonstrate in-plane scanners and fast translational vertical mirrors fabricated using these processes. In addition, we propose extensions of the fabrication process to account for DRIE aspect-ratio limitations. Mask layouts of key SOB building blocks, including vertical mirrors, beam splitters, and parallel-plate actuators, are also presented.$hfill$ [2008-0146]      

Fabrication of Flexible Transducer Arrays With Through-Wafer Electrical Interconnects Based on Trench Refilling With PDMS

Flexible transducer arrays are desired to wrap around catheter tips for side-looking intravascular ultrasound imaging. We present a technique for constructing flexible capacitive micromachined ultrasonic transducer (CMUT) arrays by forming polymer-filled deep trenches in a silicon substrate. First, we etch deep trenches between the bottom electrodes of CMUT elements on a prime silicon wafer using deep reactive ion etching. Second, we fusion-bond a silicon-on-insulator (SOI) wafer to the prime silicon wafer. Once the silicon handle and buried oxide layers are removed from the back side of the SOI wafer, the remaining thin silicon device layer acts as a movable membrane and top electrode. Third, we fill the deep trenches with polydimethylsiloxane, and thin the wafer down from the back side. The 16 by 16 flexible 2-D arrays presented in this paper have a trench width that varies between 6 and 20 ; the trench depth is 150 ; the membrane thickness is 1.83 ; and the final substrate thickness is 150 . We demonstrate the flexibility of the substrate by wrapping it around a needle tip with a radius of 450 (less than catheter size of 3 French). Measurements in air validate the functionality of the arrays. The 250- by 250- transducer elements have a capacitance of 2.29 to 2.67 pF, and a resonant frequency of 5.0 to 4.3 MHz, for dc bias voltages ranging from 70 to 100 V.     

Micromachined flat-walled valveless diffuser pumps

The first valveless diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE) is presented. The pump was fabricated in a two-mask micromachining process in a silicon wafer polished on both sides, anodically bonded to a glass wafer. Pump chambers and diffuser elements were etched in the silicon wafer using DRIE, while inlet and outlet holes are etched using an anisotropic etch. The DRIE etch resulted in rectangular diffuser cross sections. Results are presented on pumps with different diffuser dimensions in terms of diffuser neck width, length, and angle. The maximum pump pressure is 7.6 m H₂O (74 kPa), and the maximum pump flow is 2.3 ml/min for water     

Design and fabrication of a new MEMS capacitive microphone using a perforated aluminum diaphragm

In this paper, a novel single-chip MEMS capacitive microphone is presented. The novelties of the method relies on the moveable aluminum (Al) diaphragm positioned over the backplate electrode, where the diaphragm includes a plurality of holes to allow the air in the gap between the electrode and the diaphragm to escape and thus reducing acoustical damping in the microphone. Spin-on-glass (SOG) was used as a sacrificial and isolating layer. Backplate is monocrystalline silicon wafer, that it is more stiff. This work will focus on design, simulation, fabrication and characterization of the microphone. The structure has a diaphragm thickness of 3 μm, a diaphragm size of 0.5 mm × 0.5 mm, and an air gap of 1.0 μm. The results show that the pull-in voltage is 105 V, the initial stress of evaporated aluminum diaphragm is around 1500 MPa and the zero bias capacitance of microphone is 2.12 pF. Comparing with the previous works, this microphone has several advantages: the holes have been made on diaphragm, therefore no need of KOH etching to make back chamber, in this way the chip size of each microphone is reduced. The fabrication process uses minimal number of layers and masks to reduce the fabrication cost.     

Formation of homogenous nanofibers using silicon microneedle spinnerets

We report the use of a silicon microfabricated device as a new spinneret for electrospinning purposes. This device has been realized on silicon substrates using a deep reactive ion etching process. To make proper holes in the center of microneedles, a rotating angle deposition method followed by vertical etching of silicon is employed. By using these needles as fluid nozzles in the electrospinning process, poly vinyl alcohol solution with a concentration of 7?% has been converted into nanofibers. The formation of nanofibers has been investigated using field emission scanning electron microscopy. Using this process, nanofibers with a diameter of 100–200?nm are realized where the dispersion is less than 50?nm. Finally, the effects of needle size and the applied voltage have been investigated on the diameter of nanofibers.     

Angular vertical comb actuators assembled on-chip using in-plane electrothermal actuators and latching mechanisms

We have designed, fabricated and tested self-aligned angular vertical comb-drive (AVC) actuators by on-chip assembly using in-plane electrothermal actuators and latching mechanisms. The on-chip assembly process is carried out by engaging latching mechanism connected to the torsion bars through the off-centered thinned down silicon beams. When the latching mechanism is fully engaged, the assembled AVC actuator forms permanent initial tilt angle by the retraction force of electrothermal actuators. The AVC actuators and latching mechanisms are fabricated on a silicon-on-insulator (SOI) wafer using three photomasks and three times of deep etch steps. The maximum optical scan angle of 30.7° is achieved at 4.56 kHz under the sinusoidal driving voltage of 0–80 V applied to the AVC actuator. After the reliability test performed by operating the actuator for 1.6 × 10⁸ cycles at its resonance, the measured optical scan angle variation and resonant frequency change were within 1.1% and 8 Hz, respectively, and the robustness of the latched mechanism was ensured.     

Real-time etch-depth measurements of MEMS devices

An in situ, real-time process control tool was developed for MEMS deep reactive-ion etch (DRIE) fabrication. DRIE processes are used to manufacture high-aspect-ratio silicon structures up to several hundred microns thick, which would be difficult or impossible to produce by other methods. DRIE MEMS technologies promise to deliver new devices with increased performance and functionality at lower cost. A major difficulty with DRIE is the control of etch depth. Our research shows that it is possible to monitor the etch depth of various MEMS structures (holes, pillars, trenches, etc.) through measurement and analysis of the infrared reflectance spectrum. Depths as large as 150 μm have been measured. Excellent correlation is found between the etch depths determined by analysis of these measurements and those measured with an SEM. In addition to etch depth, other parameters such as the photoresist thickness (e.g., mask erosion) can be simultaneously extracted. Based on these results, an infrared-reflectance etch monitor was integrated onto a reactive ion etcher at the Berkeley Sensor and Actuator Center for real-time monitoring and end-point determination. The integrated optical metrology system demonstrated accurate real-time monitoring of the etch depth and photoresist mask erosion     

Efficient organic light-emitting diodes with C60 buffer layer

Organic light-emitting diodes (OLEDs) with C₆₀ buffer layer were fabricated. The effect of C₆₀ buffer layer on the performance of the devices was investigated by inserting C₆₀ buffer layer at the interface between the electrode and organic layers. The device structures were (1) ITO/C₆₀ (0.0, 0.4, 0.7 and 1.0 nm)/NPB/Alq₃/LiF/Al and (2) ITO/NPB/Alq₃/C₆₀ (0.0, 0.4, 0.7 and 1.0 nm)/LiF/Al. The highest brightness and efficiency of the device (1) with 0.7 nm-thick C₆₀ layer reached 6439 cd/m² at 16 V and 1.80 cd/A at 6.4 V, respectively. The enhancements in brightness and efficiency are attributed to an improved balance of hole and electron injections due to C₆₀ layer blocking parts of the injected holes. On the contrary, the brightness and efficiency of the devices with the structure (2) had been hardly enhanced.     

Deep Vertical Etching of Silicon Wafers Using a Hydrogenation-Assisted Reactive Ion Etching

A novel hydrogenation-assisted deep reactive ion etching of silicon is reported. The process uses sequential hydrogen-assisted passivation and plasma etching at low-density plasma powers to stimulate the vertical removal of the exposed Si substrate. The main feature of this technique is the sequential alternation of the electrodes while switching between different gases. Three-dimensional structures with aspect ratios in excess of 40:1 and features as small as 0.7 mum have been realized. The net etch rate is about 0.25 mum/min, although higher rates are expected to be achievable.     

Study of silicon backside damage in deep reactive ion etching for bonded silicon–glass structures

 For devices of bonded silicon and glass structures fabricated by deep reactive ion etching (DRIE), it is important to avoid damage at the silicon sidewall and backside during through-wafer etching in order to ensure reliability of devices. The silicon damage caused by charge accumulation at the glass surface is inhibited by means of an electrically conducting layer patterned onto the glass and connected with the silicon. In this study, indium tin oxide films were applied in order to identify the positions of silicon damage in the structural layout without destruction of samples. From the results, we report that there exists silicon damage caused by charge accumulation at the silicon islands divided by DRIE and we present important rules for mask layout when utilizing this method. Received: 10 August 2001/Accepted: 24 September 2001 This paper was presented at the Fourth International Workshop on high Aspect Ratio Microstructure Technology HARMST 2001 in June 2001.     

Tolerance analysis for comb-drive actuator using DRIE fabrication

Deep reactive ion etching (DRIE) process is specially invented for bulk micromachining fabrication with the objective of realizing high aspect ratio microstructures. However, various tolerances, such as slanted etched profile, uneven deep beams and undercut, cannot be avoided during the fabrication process. In this paper, the origins of various fabrication tolerances together with its effects on the performances of lateral comb-drive actuator, in terms of electrostatic force, mechanical stiffness, stability and displacement, are discussed. It shows that comb finger with positive slope generates larger electrostatic force. The mechanical stiffness along lateral direction increases when the folded beam slants negatively. The displacement is 4.832 times larger if the comb finger and folded beam are tapered to +1° and −1°, respectively. The uneven deep fingers generate an abrupt force and displacement when the motion distance reaches the initial overlap length. The undercut reduces both the driving force and the mechanical stiffness of the lateral comb-drive actuator. The fabricated comb-drive actuator, with comb finger of +1° profile and 0.025 μm undercut, and folded beam of −1° slope and 0.075 μm undercut, is measured and compared with the models where both show consistent results. These analytical results can be used to compensate the fabrication tolerances at design stage and allow the actuators to provide more predictable performance.     

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-$mu$m Openings

This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub-$mu$m regime, while the only lithography step involved has$mu$m-scale resolution. This thick oxide mask layer with sub-$mu$m openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5-$mu$m-thick oxide layer, while the original lithographically defined feature sizes are larger than 1$mu$m in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub-$mu$m capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented.1684