Eccentricity estimation with error modeling in dynamic wafer handling

Wafer-handling robots are used to transfer wafers in semiconductor manufacturing. Typically, a pick–measure–place method is used to transfer wafers accurately between stations. The measurement step is performed using an aligner, which is time-consuming. To increase the wafer transfer efficiency, it is desirable to speed up the measurement process or place it in parallel with other operations. Hence, optic sensors are installed at each station to estimate the wafer eccentricity on the fly. The eccentricity values are then used to control the robot to place the wafer directly onto another station accurately without using the aligner. In this paper, the kinematic model of a wafer-handling robot is developed. The errors in the kinematics model are analyzed. A model parameter identification method is proposed to obtain the parameters. A wafer eccentricity identification method is derived to calculate the eccentricity values on the fly. Experiments were performed to validate the proposed methods. The computed eccentricity errors are compared with those obtained by other researchers. The results demonstrated that the kinematics error modeling method can increase the wafer eccentricity identification accuracy. Hence, the developed methods can be applied to estimate the wafer eccentricity on the fly to reduce the wafer transfer cycle time and increase wafer-handling efficiency.     

Signal analysis and real-time monitoring for wafer polishing processes using the ch computing environment

There are several processes used in the silicon wafer fabrication industry to achieve the planarity necessary for photolithography requirements. Polishing is one of the important processes which influence surface roughness in the manufacturing of silicon wafers. As the level of a silicon wafer surface directly affects device line-width capability, process latitude, yield, and throughput in the fabrication of microchips, it is necessary for it to have an ultra precision surface and flatness. The surface roughness in wafer polishing is affected by many process parameters. To decrease the surface roughness of the wafer, controlling the polishing parameters is very important. Above all, a real-time monitoring technology of the polishing parameters is necessary for the control. In this study, parameters affecting the surface roughness of the silicon wafer are measured in real-time. In addition comparing the predicted value is done according to the process parameters using the artificial neural network. Through these results, we conduct research on the efficient parameters of silicon wafer polishing. Required programs are developed using the Ch computing environment.     

一种快速检测单晶硅亚表面损伤层厚度的方法

为了保证单晶硅晶圆在精研与抛光过程中的品质与质量,亟待寻求一种快速、简单、经济的硅材料亚表面损伤程度的检测方法。基于HF溶液对单晶硅损伤层的选择性刻蚀特性,提出一种快速检测单晶硅亚表面损伤层厚度的方法。透射电镜观测结果显示,HF溶液能选择性地刻蚀单晶硅划痕区域的亚表面损伤层,证实了该方法检测结果的有效性。利用该方法研究了载荷和速度对单晶硅亚表面划痕损伤的影响。结果表明,当外加载荷为单晶硅临界屈服载荷的1.1倍及以下时,单晶硅亚表面的划痕损伤层厚度随刻画速度的增大而减小;而当外加载荷达到临界屈服载荷的12.5倍时,单晶硅亚表面的划痕损伤对刻画速度的变化不敏感。该方法可方便快捷地检测单晶硅划痕区域亚表面的损伤层厚度,有望应用于单晶硅晶圆平坦化过程的损伤检测与控制。     

Effects of support method and mechanical property of 300 mm silicon wafer on sori measurement

This paper describes the effects of support methods and mechanical properties of 300 mm silicon wafer on sori measurement. A new supporting method, named three-point-support method, used in the sori measurement of a large diameter silicon wafer was proposed in this study to obtain a more stable measuring process. The wafer was supported horizontally by three steel balls on the vertexes of a regular triangle at the wafer edge. The measuring repeatability and anti-disturbance ability were compared between the proposed method and the conventional one-point-support method, in which the wafer is supported with a small-area chuck at the wafer center. The effects of friction between the supports and wafer surface for the three-point-support were also estimated. Finally, the influences of different mechanical characteristics at the front and back surfaces and the crystal orientation on sori measurement were investigated.     

A study on the characteristics of a wafer-polishing process according to machining conditions

The polishing process for silicon wafers plays a key role in the fabrication of semiconductors, since a globally planar, mirrorlike wafer surface is achieved in the process. The surface roughness of the wafer depends on the surface properties of the carrier head unit, together with other machining conditions, such as working speed, type of polishing pad, temperature, and down force. In this paper, the results of several experiments are used to study silicon wafer surfaces. The experiments were designed to observe the down force and temperature when a wafer carrier head unit with wafer was pressed down onto a polishing pad. A load cell was employed to detect the applied pressure against the polishing pad, and the working temperature was measured with an infrared sensor. Wafer surface roughness was investigated according to several parameters and experimental data.     

RESPONSE SURFACE ANALYSIS OF SLICING OF SILICON INGOTS WITH FOCUS ON PHOTOVOLTAIC APPLICATION

Polycrystalline silicon wafers are widely used in Photovoltaic (PV) industry as a base material for the solar cells. The existing silicon ingot slicing methods typically provide minimum wafer thickness of 300–350 μm and a surface finish of 3–5 μm R_a while incurring considerable kerf loss of 35–40%. Consequently, efficient dicing methods need to be developed, and in the quest for developing new processes for silicon ingot slicing, the wire-EDM (electric discharge machining) is emerging as a potential process. Slicing of a 3′′ square silicon ingot into wafers of 500 μm in thickness has been performed to study the process capability. This article analyzes the effect of processing parameters on the cutting process. The objective of the experimental study is improvement in slicing speed, minimization of kerf loss and surface roughness. A central composite design-based response surface methodology (RSM) has been used to study the slicing of polycrystalline silicon ingot via wire-EDM. A zinc-coated brass wire, 100 μm in diameter, has been used as an electrode in the slicing experiments. It has been observed that the optimal selection of the process parameters results in an increase of 40–50% in the slicing rate along with a 20% reduction in the kerf loss as compared to the conventional methods. The machined surfaces on the sliced wafer were free of micro-cracks and wire material contamination, thereby making it useful for electronic applications.     

Evaluation of a wafer transportation speed for propulsion nozzle array on air levitation system

A transportation system of single wafer has been developed to be applied to semiconductor manufacturing process of the next generation. In this study, the experimental apparatus consists of two kinds of track, one is for propelling a wafer, so called control track, the other is for generating an air film to transfer a wafer, so called transfer track. The wafer transportation speed has been evaluated by the numerical and the experimental methods for three types of nozzle position array (i.e., the front-, face- and rear-array) in an air levitation system. Test facility for 300 mm wafer has been equipped with two control tracks and one transfer track of 1500 mm length from the starting point to the stopping point. From the present results, it is found that the experimental values of the wafer transportation speed are well in agreement with the computed ones. Namely, the computed values of the maximum wafer transportation speed Vmax are slightly higher than the experimental ones by about 15–20%. The disparities in Vmax between the numerical and the experimental results become smaller as the air velocity increases. Also, at the same air flow rate, the order of wafer transportation speeds is: V_max for the front-array > V_max for the face-array > V_max for the rear-array. However, the face-array is rather more stable than any other type of nozzle array to ensure safe transportation of a wafer.     

工件旋转法磨削硅片的磨粒切削深度模型

半导体器件制造中,工件旋转法磨削是大尺寸硅片正面平坦化加工和背面薄化加工最广泛应用的加工方法。磨粒切削深度是反映磨削条件综合作用的磨削参量,其大小直接影响磨削工件的表面/亚表面质量,研究工件旋转法磨削的磨粒切削深度模型对于实现硅片高效率高质量磨削加工具有重要的指导意义。通过分析工件旋转法磨削过程中砂轮、磨粒和硅片之间的相对运动,建立磨粒切削深度模型,得到磨粒切削深度与砂轮直径和齿宽、加工参数以及工件表面作用位置间的数学关系。根据推导的磨粒切削深度公式,进一步研究工件旋转法磨削硅片时产生的亚表面损伤沿工件半径方向的变化趋势以及加工条件对磨削硅片亚表面损伤的影响规律,并进行试验验证。结果表明,工件旋转法磨削硅片的亚表面损伤深度沿硅片半径方向从边缘到中心逐渐减小,随着砂轮磨粒粒径、砂轮进给速度、工件转速的增大和砂轮转速的减小,加工硅片的亚表面损伤也随之变大,试验结果与模型分析结果一致。     

Analysis of silicon via hole drilling for wafer level chip stacking by UV laser

For stacking wafers/dies, through-silicon-vias (TSVs) need to be created for electrical connection of each wafer/die, which enables better electrical characteristics and less footprints. And for via hole processing, chemical methods such as DRIE (Deep Reactive Ion Etching) are mostly used. These methods suffer the problems of slow processing speed, being environment-unfriendly and damage on the existing electric circuits due to high process temperature. Furthermore, masks are also needed. To find an alternative to the methods, researches on the laser drilling of via holes on silicon wafer are being conducted. This paper investigates the silicon via hole drilling process using laser beam. The percussion drilling method is used for this investigation. It is also examined how the laser parameters- laser power, pulse frequency, the number of laser pulses and the diameter of laser beam- have an influence on the drilling depth, the hole diameter and the quality of via holes. From these results, laser drilling process is optimized. The via hole made by UV laser on the crystal silicon wafer is 100μm deep, has the diameter of 27.2μm on the top, 12.9μm at the bottom. These diameters deviate from the target values by 2.8μm and 0.4μm respectively. These values correspond to the deviation from the target taper angle of the via hole by less than 1°. The processing speed of the laser via hole drilling is 114mm/sec, therefore, etching process can be replaced by this method, if the number of via holes on a wafer is smaller than 470,588. The ablation threshold fluence of silicon is also determined by a FEM model and is verified by experiment.     

双机械手变速协同输送控制策略研究及应用

基于智能先进、高效稳定的制造理念,针对双机械手接续输送物料同步交接的问题,提出了一种在有限交接区间限制条件下的高效双机械手协同工作的快速输送方法。通过运动学分析,设计构建了双机械手协同输送实验平台,研究了多种可行方案中影响快速同步的主要因素,给出了多种协同输送工作方法的实现过程。考虑到速度与稳定性的综合指标,以及最小同步交接距离的需要,采用两级变速控制同步方法,板料输送节拍缩短超过11%。     

干摩擦和水润滑条件下单晶硅的摩擦磨损性能研究

在UMT-2微摩擦试验机上,对单晶硅片进行了干摩擦和水润滑两种状态下的摩擦磨损试验,分析讨论了载荷和滑动速度对单晶硅片的摩擦因数和磨损率的影响规律;运用扫描电子显微镜,观察和分析了其磨损表面形貌。结果表明:干摩擦条件下的磨损机理主要表现为黏着磨损,水润滑条件下的磨损机理主要表现为机械控制化学作用下的原子/分子去除过程;水润滑条件下的摩擦因数和磨损量均较小,最小磨损率仅为10μm3/s;在水润滑条件下,载荷和滑动速度达到一定值时,硅片表面将发生摩擦化学反应,生成具有润滑作用的Si(OH)4膜,即机械作用在一定条件下对化学反应具有促进作用。     

A novel method for effective sodium ion implantation into silicon

Although sodium ion implantation is useful to the surface modification of biomaterials and nano-electronic materials, it is a challenging to conduct effective sodium implantation by traditional implantation methods due to its high chemical reactivity. In this paper, we present a novel method by coupling a Na dispenser with plasma immersion ion implantation and radio frequency discharge. X-ray photoelectron spectroscopy (XPS) depth profiling reveals that sodium is effectively implanted into a silicon wafer using this apparatus. The Na 1s XPS spectra disclose Na(2)O-SiO(2) bonds and the implantation effects are confirmed by tapping mode atomic force microscopy. Our setup provides a feasible way to conduct sodium ion implantation effectively.     

现代离子注入机的机械扫描技术

简单介绍了典型离子注入机的组成,分析了离子注入机中扫描技术的重要性。随着集成电路工艺技术的提高,对离子注入提出更高的要求,传统的批注入已不能满足当前的工艺,从而开发出了适应当前工艺的单晶片注入的机械扫描技术。这种注入技术解决了技术上的难题,也很好地控制了成本风险,同时具有更高精度、更少污染等一系列优点,成为当前高端离子注入机机械扫描技术的首选。本文对国内外技术进行了对比,对国内离子注入机机械扫描技术的发展进行了展望。     

Wear of single crystal silicon as a function of surface roughness

With increasing activities on micro electro-mechanical systems (MEMS) type microactuators, there is a growing need in understanding the tribological properties of silicon, the most commonly used wafer material for those devices. In particular, it is of interest if single crystal silicon used in microactuators exposed to rather low vertical loads is subject to wear. Therefore, wear tests using monocrystalline silicon on both sides of the tribological interface were conducted.A classic way to measure wear on sliders in contact with a tape or a rotating disk is to create an imprint using a Berkovich diamond tip mounted on a picoindenter. However, in our case we used a different approach. We created three studs on a slider’s surface by recessing the material outside the studs through an ion milling process. During the wear tests, the studs wore off. By measuring the remaining stud height, the wear volume could be determined at any point in time. The tests were performed on a pin on disk tester with a gimbaled slider to realize a flat on flat contact and a rather low normal force of 30 mN.     

内置皮拉尼计的硅通孔圆片级MEMS真空封装研究

针对现有的圆片级真空封装存在检测难、易泄漏等问题,提出了内置皮拉尼计的硅通孔圆片级MEMS真空封装方法。研制了用于圆片级真空封装导线互连的硅通孔,探讨了玻璃盖板与硅圆片之间阳极键合工艺与硅圆片与硅圆片之间的金硅共晶键合工艺,研制了用于检测封装壳体内部真空度的皮拉尼计; 研制了内置皮拉尼计的4英寸硅通孔圆片级真空封装,研制了低温激活非蒸散型吸气剂。实验研究表明,该研究解决了长时间保持真空度的问题。     

微电铸工艺中含N’N-二乙基硫脲添加剂时金属铜填洞机理研究

为了研究含N’N-二乙基硫脲添加剂的微电铸工艺金属铜填洞机理,本文采用线性伏安法、循环电压电流溶出法(CVS)、扫描电镜(SEM)以及XRD测量法研究N’N-二乙基硫脲对微电铸工艺电化学行为的影响,并借助塔菲尔方程,研究微电铸铜反应过程中的电极动力学参数。结果显示：当微电铸铜工艺中加入N’N-二乙基硫脲添加剂时,产生活性极化,提高了铜离子还原时所需的活化能,金属离子的放电速度从2.2214 mA/ cm2降低 到约0.076 mA/ cm2,这样增加了反应时的过电位,促使电极表面晶核成型速度增加,晶体成长速度由2.57μm /min 降低到约0.17μm /min,铜离子的平滑能力提高约50%。这样可以有效减小微电铸时的边沿效应,使金属铜具有良好的填充微型孔洞的能力。本实验通过微电铸工艺成功地将金属铜填充入宽为10μm,深宽比为4：1的微型凹槽中,且镀层内没有空洞、空隙以及细缝等缺陷。     

单晶片离子注入机垂直扫描机构的差分密封设计

垂直扫描机构是单晶片离子注入机靶盘的支撑部件,起着将高速直线运动从靶室外传递到靶盘的作用.文中针对垂直扫描机构进行了差分密封的设计和计算,结果显示,此垂直扫描机构具有无摩擦、漏气率小的特点,因此它能满足晶片处理过程中对靶室高真空度及金属颗粒的要求.     

A state-of-the-art review of ductile cutting of silicon wafers for semiconductor and microelectronics industries

Silicon is a typical functional material for semiconductor and optical industry. Many hi-tech products like lenses in thermal imaging, solar cells, and some key products of semiconductor industry are made of single crystal silicon. Silicon wafers are used as substrate to build vast majority of semiconductor and microelectronic devices. To meet high surge in demand for microelectronics based products in recent years, the development of rapid and cost efficient processes is inevitable to produce silicon wafers with high-quality surface finish. The current industry uses a sequence of processes such as slicing, edge grinding, finishing, lapping, polishing, back thinning, and dicing. Most of these processes use grinding grains or abrasives for material removal. The mechanism of material removal in these processes is fracture based which imparts subsurface damage when abrasive particles penetrate into the substrate surface. Most of these traditional processes are extremely slow and inefficient for machining wafers in bulk quantity. Moreover, the depth of subsurface damage caused by these processes can be up to few microns and it is too costly and time consuming to remove this damage by heavy chemical–mechanical polishing process. Therefore, semiconductor industry requires some alternative process that is rapid and cost effective for machining silicon wafers. Ductile cutting of silicon wafer has the potential to replace the tradition wafer machining processes efficiently. If implemented effectively in industry, ductile cutting of silicon wafers should reduce the time and cost of wafer machining and consequently improve the productivity of the process. This paper reviews and discusses machining characteristics associated with ductile cutting of silicon wafers. The limitations of traditional wafer fabrication, the driving factors for switching to ductile cutting technology, basic mechanism of ductile cutting, cutting mechanics, cutting forces, surface topography, thermal aspects, and important factors affecting these machining characteristics have been discussed to give a systematic insight into the technology.     

高效太阳能电池快速烧结设备的系统与工艺研究

在太阳能电池片的制作过程中,“烧结”是一道很重要的工序,其制作的过程就要用到快速烧结炉。其作用就是把印刷到硅片上的电极在高温下烧结成电池片,最终使电极和硅片本身形成欧姆接触,从而提高电池片的开路电压和填充因子2个关键参数,使电极的接触具有电阻特性,达到生产出高转换效率电池片的目的。故快速烧结炉的结构设计及工艺运行状态的好坏直接影响到电池片的质量,所以好的烧结设备的设计和烧结工艺是密不可分的。本文详述了高效太阳能电池快速烧结设备的部件设置,并对设备进行剖析,说明设计精良的烧结设备是工艺提升的基础。     

基于RSM的SiC单晶片表面粗糙度预测及参数优化

通过响应面分析法(RSM)对超声振动辅助金刚石线锯切割SiC单晶体的工艺参数进行分析和优化。采用中心组合设计实验,考察线锯速度、工件进给速度、工件转速和超声波振幅这4个因素对SiC单晶片表面粗糙度值的影响,建立了SiC单晶片表面粗糙度的响应模型,进行响应面分析,采用满意度函数(DFM)确定了切割SiC单晶体的最佳工艺参数,验证试验表明该模型能实现相应的硬脆材料切割过程的表面粗糙度预测。