高K栅介质/金属栅极金属氧化物半导体晶体管平带电压roll-off现象物理起源研究

本文从能带平衡的角度来研究带有高K栅介质/金属栅极的金属氧化物半导体晶体管平带电压roll-off现象,认为随着高K介质与Si衬底之间中间层厚度的减小,高K介质与Si之间直接的电子交换会从无到有,越来越强,而这可能是roll-off现象的起源之一。此外给出了在不同条件下基于此模型得到的理论模拟结果。     

Low-Power FPGA-Implementation of <Emphasis Type="Italic">atan</Emphasis>(<Emphasis Type="Italic">Y</Emphasis>/<Emphasis Type="Italic">X</Emphasis>) Using Look-Up Table Methods for Communication Applications

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

一种模糊-证据kNN分类方法

 已有的以k-最近邻(k Nearest Neighbor,kNN)规则为核心的分类算法,如模糊kNN(Fuzzy kNN,FkNN)和证据kNN (Evidential kNN,EkNN)等,存在着两个问题:无法区别出样本特征的差异以及忽略了邻居距训练样本类中心距离的不同所带来的影响.为此,本文提出一种模糊-证据kNN算法.首先,利用特征的模糊熵值确定每个特征的权重,基于加权欧氏距离选取k个邻居;然后,利用邻居的信息熵区别对待邻居并结合FkNN在表示信息和EkNN在融合决策方面的优势,采取先模糊化再融合的方法确定待分类样本的类别.本文的方法在UCI标准数据集上进行了测试,结果表明该方法优于已有算法.     

Influence of substrate thickness on thermal impedance of microelectronic structures

The thermal impedance Z_th(jω) has been calculated numerically, using the boundary element method, for a silicon substrate with a uniform heat source on top. The key feature is that the dynamic thermal behaviour is calculated directly in the frequency domain. The calculations were performed for a wide range of values for the thickness of the substrate. By representing the thermal impedance in a Nyquist plot (i.e. Im[Z_th(jω)] vs. Re[Z_th(jω)] with ω as parameter), mainly two circular arcs are observed. For the lower frequency arc, the impedance values as well as the frequency scale are found to be largely influenced by the substrate thickness. The arc corresponding to high frequencies on the other hand remains unchanged under thickness variations.Further analysis revealed an almost perfectly linear relationship between the thermal resistance R_th = Z_th(jω = 0) and the substrate thickness, even when the heat source is not centred on the substrate. Both the slope and intersection value obtained from the curve fitting can be explained by a simple geometrical model including the fixed-angle heat spreading approximation, used since many years in the literature.     

Air-Gaps for High-Performance On-Chip Interconnect Part II: Modeling, Fabrication, and Characterization

Air-gaps are the ultimate low-k material in microelectronics due to air having a low dielectric constant close to 1.0. The interconnect capacitance can further be reduced by extending the air-gaps into the interlayer dielectric region to reduce the fringing electric field. An electrostatic model (200 nm half-pitch interconnect with an aspect ratio of 2.0), was used to evaluate the dielectric properties of the air-gap structures. The incorporation of air-gaps into the intrametal dielectric region reduced the capacitance by 39% compared with SiO₂. Extending the air-gap 100 nm into the top and bottom interlayer SiO₂ region lowered the capacitance by 49%. The ability to fabricate air-gaps and ‹extended air-gaps’ was demonstrated, and the capacitance decrease was experimentally verified. Cu/air-gap and extended Cu/air-gap interconnect structures were fabricated using high-modulus tetracyclododecene (TD)-based sacrificial polymer. The aspect ratio of the air-gap was 1.8 and the air-gap was extended 80 nm and 100 nm into the top and bottom interlevel SiO₂ region, respectively. The measured effective dielectric constant (k _eff) of the Cu/air-gap and the extended Cu/air-gap structures with SiO₂ interlevel dielectric was 2.42 and 2.17, respectively. The effect of moisture uptake within the extended Cu/air-gap structure was investigated. As the relative humidity increased from 4% to 92%, the k _eff increased by 7%. Hexamethyldisilazane was used to remove adsorbed moisture and create a hydrophobic termination within the air-cavities, which lowered the effect of humidity on the k _eff. A dual Damascene air-gap and extended air-gap fabrication processes were proposed and the challenges of using a sacrificial polymer placeholder approach to form air-cavities are compared to other integration approaches of dual Damascene air-gap.     

Compressed error and erasure correcting codes via rank‐metric codes in random network coding

The error control of random network coding has recently received a lot of attention because its solution can increase robustness and reliability of data transmission. To achieve this, additional overhead is needed for error correction. In this paper, we design a compressed error and erasure correcting scheme to decrease the additional overhead of error correction. This scheme reduces the computation overhead dramatically by employing an efficient algorithm to detect and delete linearly dependent received packets in the destination node. It also simplifies the hardware operations when the scheme reduces the received matrix Y to form E_k(Y ) instead of E(Y ) in the decoding process. If at most r original packets get combined in k packets of one batch, the payload of one packet can increase from M ? k to M ? O(rlog _qk) for the application of compressed code, where M is the packet length. In particular, the decoding complexity of compressed code is O(rm) operations in an extension field , which does not enhance the overall decoding complexity of the system. Finally, we also compare our scheme's performance with existing works. The numerical results and analyses illustrate the security and performance of our scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

ZrAlO ternary oxide as a candidate for high-k dielectrics

ZrAlO thin films were prepared by the pyrosol process. Four different cases were considered taking as basis a solution of 0.025 M zirconium acetylacetonate (ZrAAc) and 5 at% of aluminum acetylacetonate (AlAAc) dissolved in pure methanol. Films of case A, were deposited with the mentioned solution and subjected to rapid thermal annealing (RTA). For case B, a small volume of water was added to start solution. Case C, were similar samples of case B, but with a post-deposition RTA. Case D, were Si/Al₂O₃/ZrAlO/Al stacks with post-deposition RTA, using water in the start solution. XPS profiles show that the relative chemical composition of deposited materials is affected by the volume of water added (Vw). The aluminum concentration in the films acquires values as high as or higher than zirconium concentration for increasing Vw. All the prepared samples were amorphous as indicated by the X-ray diffraction (XRD) spectra, even for large integration times. Current–voltage (I–V) and capacitance measurements were carried out in metal–insulator–metal (MIM) devices (Corning-glass/TCO/ZrAlO/Al) and I–V and simultaneous capacitance–voltage (C–V) measurements were performed in metal–oxide–semiconductor (MOS) devices (Si/ZrAlO/Al and Si/Al₂O₃/ZrAlO/Al). Leakage currents of the order of 10⁻⁴ A/cm², were typically obtained in MIM devices, whereas for some MOS devices, leakage currents of the order of 10⁻⁷ A/cm² were obtained. Dielectric constant (k) values of the order of 24 were calculated for MIM devices and k values ranging from 12.5 up to 17 were calculated for MOS devices.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

Phase stabilization of sputtered strontium zirconate

In this paper we present the investigation of high-k dielectrics in a metal-insulator-metal structure. We show the physical and electrical properties of ZrO₂ and Sr_xZr_(1−x)O_y grown through sputter deposition. Uncontrolled crystallization of ZrO₂ during the growth into a mixture of different phases was observed. As a consequence, the k-value was suppressed. Stabilization of the amorphous phase of the as grown films could be achieved by the admixture of SrO. This enabled controlled crystallization into a single phase after performing post-deposition annealing. The k-value of the annealed Sr_xZr_(1−x)O_y was determined to be 33.     

Partial Fraction Decomposition and Correlation Sequence in 2D Systems

In this paper, results of the one-dimensional (1D) digital filtering are extended to the two-dimensional (2D) case. It introduces a technique and an algorithm for the computation of the product H(z₁,z₂)H(z₁⁻¹,z₂⁻¹). The technique is used to find a minimum phase transfer function of a 2D system such that the previous product matches a given correlation sequence. The algorithm requires less arithmetic operations than the traditional methods. The former is based on a matrix formulation of the product, which is used to investigate the 2D partial fraction decomposition (PFD) and stability.     

Dielectric anisotropy in the integration of Cu-SiLK™ system

As device density and performance continue to improve, low dielectric constant (k) materials are needed for interlevel dielectric (ILD) applications. The dielectric anisotropy of polymers with low k is an important property to consider for developing ILD. This is on-going research on the integration aspects of Cu-SiLK™ system. In this study, the dielectric anisotropy of SiLK polymer was evaluated with two test structures: the metal-insulator-metal (MIM) parallel capacitor structure for the out-of-phase dielectric constant (k_⊥) and comb-and-serpentine interdigitated structure for the in-plane dielectric constant (k_∥). A k_⊥ of 2.65, a k_∥ of 2.75, and a dielectric anisotropy of 3.77% were obtained for SiLK. However, SiLK exhibits larger leakage current as compared to amorphous SiO₂ films. The reliability issue on the integration of Cu-SiLK is discussed.     

Directedk-hypertree method for hypernetwork analysis

The directed hypergraph theory is presented, and by applying it the directedk-hypertree method for hypernetwork analysis is derived. Using this method the scale of electrical networks which can be topologically analysed by a computer will be increased, and the resultant expressions are compact.     

Influence of post deposition annealing on Y2O3-gated GaAs MOS capacitors and their reliability issues

The feasibility of employing yttrium oxide (Y₂O₃) as high-k gate dielectrics for GaAs metal-oxide-semiconductor (MOS) devices has been investigated. MOS capacitors were fabricated using RF-sputtered deposited Y₂O₃ films on NH₄OH treated n-GaAs substrate. Indeed high-k (Y₂O₃)/GaAs MOS capacitors exhibiting fairly good electrical characteristics, for instance, especially low leakage current density, low hysteresis and allowable density of interface states, have been achieved. The effects of several annealing treatments on Y₂O₃-gated GaAs MOS capacitors have been investigated in order to optimize the process conditions. A decrease in accumulation capacitance (C_acc) following PDA effectively increases the equivalent oxide thickness (EOT), which is predicted to be correlated with the growth and continuous increase in the physical thickness of a lower-k inter-layer sandwiched between Y₂O₃ and GaAs. However, leakage currents and interface trap densities are reduced with higher values of annealing temperature. The variation of current density with an equivalent oxide thickness (EOT) has also been investigated.     

Analysis of the composition of (Al,Ga)As alloys by secondary ion mass spectroscopy and X-ray diffractometry

Calibration lines for the layer-by-layer analysis of the concentration of matrix elements in Al _x Ga_{1 ? x} As layers are obtained using a TOF.SIMS-5 secondary-ion mass spectrometer. The alloy concentration for the set of test samples was independently measured by high-resolution X-ray diffractometry allowing for deviation of the lattice constants and elastic moduli from Vegard??s law. It is shown that when using Cs⁺ sputtering ions and a Bi⁺ beam in secondary-ion mass spectrometry, the dependence of the intensity ratio Y(CsAl⁺)/Y(CsAs⁺) on x(AlAs) is close to linear for positive ions; and when detecting negative ions, the dependence Y(Al₂As^?)/Y(As^?) on x is close to linear. These data allow us to normalize the profiles of layer-by-layer analysis in the Al _x Ga_{1 ? x} As/GaAs system. In addition, a simple variant for the introduction of corrections to the deviation from Vegard??s law in the X-ray data is suggested.     

Bounded-distance multi-clusterhead formation in wireless ad hoc networks

We present a clustering technique addressing redundancy for bounded-distance clusters, which means being able to determine the minimum number of cluster-heads per node, and the maximum distance from nodes to their cluster-heads. This problem is similar to computing a (k, r)-dominating set, (k, r)-DS, of the network. (k, r)-DS is defined as the problem of selecting a minimum cardinality vertex set D of the network such that every vertex u not in D is at a distance smaller than or equal to r from at least k vertices in D. In mobile ad hoc networks (MANETs), clusters should be computed distributively, because the topology may change frequently. We present the first centralized and distributed solutions to the (k, r)-DS problem for arbitrary topologies. The centralized algorithm computes a (k · ln Δ)-approximation, where Δ is the largest cardinality among all r-hop neighborhoods in the network. The distributed approach is extended for clustering applications, while the centralized is used as a lower bound for comparison purposes. Extensive simulations are used to compare the distributed solution with the centralized one. As a case study, we propose a novel multi-core multicast protocol that applies the distributed solution for the election of cores. The new protocol is compared against PUMA, one of the best performing multicast protocols for MANETS. Simulation results show that the new protocol outperforms PUMA on the context of static networks.     

电子束辐照下的石墨烯上的原子层沉积Al2O3介质层

为了研究石墨烯与高k介质的结合,使用原子层沉积氧化铝在石墨衬底上。沉积前使用电子束辐照,观测到了氧化铝明显改善的形貌。归因于电子束辐照过程中的石墨层的无定形变化过程。     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.