A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

AC versus DC hot-carrier degradation in n-channel MOSFETs

The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies     

A study of hot-carrier-induced mismatch drift: a reliability issuefor VLSI circuits

The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences of hot-carrier effects on gate capacitance variation and its impact on the mismatch drift of MOS dynamic circuits. It is shown here that the impact of hot-carrier-induced gate capacitance variation on VLSI circuits is more critical than DC parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64 Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carrier stress     

RF circuit performance degradation due to soft breakdown andhot-carrier effect in deep-submicrometer CMOS technology

A systematic study of RF circuit performance degradation subject to oxide soft breakdown (SBD), and hot-carrier (HC) stress is presented in this paper. DC and RF characteristics before and after stress are extracted from the experimental data. The effects of SBD and HC stress on s-parameters, cutoff frequency, third-order interception point, and noise parameters are examined. The performance drifts of gain, noise figure, linearity, and input matching of the RF low-noise amplifier are demonstrated by SpectreRF simulation results based on measured device data     

Hot-carrier degradation behavior of N- and P-channel MOSFET's underdynamic operation conditions

An in-depth study of the dynamic hot-carrier degradation behavior of N- and P-channel MOS transistors was performed based on the change of charge pumping and I-V characteristics. It is shown that for transistors with channel lengths ranging from 2 to 0.5 μm and frequencies up to 100 MHz the degradation under dynamic stress can completely be described as a quasi-static degradation, provided all static degradation effects are taken into account in the appropriate way. This means that the influence of post-stress effects and charge buildup or charge detrapping have to be considered     

Hot-carrier injection suppression due to the nitride-oxide LDDspacer structure

The hot-carrier effects in silicon nitride lightly doped drain (LDD) spacer MOSFETs are discussed. It is found that the oxide thickness under the nitride film spacer affects the hot-carrier effects. The thinner the LDD spacer oxide becomes, the larger the initial drain current degradation becomes at the DC stress test and the smaller the stress time dependence becomes. After the DC stress test, reduced drain current recovers at room temperature. These phenomena are due to the large hot-carrier injection into the LDD nitride spacer, because the nitride film barrier height is much less than the silicon oxide barrier height. Therefore, it is necessary to form the LDD spacer oxide, in order to suppress the large hot-carrier injection in the nitride film LDD spacer MOSFET. The drain current shift mechanism in the nitride spacer MOSFETs is discussed, considering the lucky electron model     

Design considerations for CMOS digital circuits with improvedhot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (τ) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability     

Low-frequency noise in hot-carrier degraded nMOSFETs

This paper discusses the low-frequency (LF) noise in submicron nMOSFETs under controlled transistor aging by hot-carrier stress. Both traditional, steady-state LF noise as well as the LF noise under periodic large-signal excitation were found to increase upon device degradation, for both hydrogen passivated and deuterium passivated Si–SiO₂ interfaces. As hot-carrier degradation is slower in deuterium-annealed MOSFETs, so is the increase of the noise in these devices. The noise-suppressing effect of periodic OFF switching is gradually lost during hot-carrier degradation, as the LF noise under periodic large-signal excitation increases more rapidly than the LF noise in steady-state.     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

Hot-carrier degradation analysis based on ring oscillators

This paper presents a new test circuit for hot-carrier degradation analysis based on a ring oscillator. The devices and the test circuit were fabricated using Philips’ 0.35 μm CMOS technology. For single device, AC and DC hot-carrier-induced degradation are the same if the effective stress time is carefully taken into account. For circuit level degradation, the frequency of the ring oscillator, on logarithmic scale degrades at the same slope as the saturation drain current of nMOS transistor degrades, while pMOS transistor degradation is much smaller than nMOSFET degradation and can be ignored. For universal applications, the circuit degradation can be expressed by MOSFETs I_dsat degradation with NSF (nMOSFET degradation speed factor) and PSF (pMOSFET degradation speed factor). Formulae for NSF and PSF calculations are derived. Simulations with Philips PSTAR circuit simulator were also performed, which well agree with the experiment results.     

A novel single-device DC method for extraction of the effectivemobility and source-drain resistances of fresh and hot-carrier degradeddrain-engineered MOSFET's

A new DC technique, the drain current-conductance method (DCCM), has been developed to extract the gate bias dependent effective channel mobility (μ_eff), and source and drain series resistance (R _s and R_d) of drain-engineered MOSFET's. The extraction of μ_eff, R_e, and R_d by DCCM is based on the DC measurements of drain current and conductance of a single device. The negligible difference between the measured and modeled (using the extracted parameters) linear drain current showed that the DCCM is accurate and effective for devices with different graded junction structures and channel lengths. Asymmetry between R_s and R_d for LDD p-MOSFET's was found to be more significant than for LATID n-MOSFET's. This asymmetry has invalidated many methods which utilized the assumptions of R_d=R_s for the extraction of device parameters. The DCCM was further applied to devices with nonuniform hot-carrier degradation. The μ_eff, R_s, and R_d of LATID n-MOSFET's degraded under different hot-carrier stress conditions were extracted. The increase in R_d is found to dominate the initial phase of hot-carrier degradation while the decrease in μ_eff intensifies as the stress duration increases. The extracted parameters have provided physical insight into the asymmetries of graded junctions and degradation mechanisms of hot-carrier stressed MOSFET's, The DCCM is especially useful for the extraction of SPICE parameters that are usable in circuit and reliability simulation     

Dynamic-stress-induced enhanced degradation of 1/f noise inn-MOSFETs

AC-stress-induced degradation of 1/f noise is investigated for n-MOSFETs with thermal oxide or nitrided oxide as gate dielectric, and the physical mechanisms involved are analyzed. It is found that the degradation of 1/f noise under AC stress is far more serious than that under DC stress. For an ac stress of V_G=0~0.5 V_D, generations of both interface states (ΔD_it) and neutral electron traps (ΔN_et) are responsible for the increase of 1/f noise, with the former being dominant. For another AC stress of V _G=0~V_D. a large increase of 1/f noise is observed for the thermal-oxide device, and is attributed to enhanced ΔN_et and generation of another specie of electron traps, plus a small amount of ΔD_it. Moreover, under the two types of AC stress conditions, much smaller degradation of 1/f noise is observed for the nitrided device due to considerably improved oxide/Si interface and near-interface oxide qualities associated with interfacial nitrogen incorporation     

An empirical model for device degradation due to hot-carrier injection

An empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented. Relationships between device degradation, drain voltage, and substrate current are clarified on the basis of experiments and modeling. The presented model makes it possible to predict the lifetime of submicron devices by determining a certain criterion, such as taking a Vthshift of 10 mV over ten years as being allowable. This could also provide quantitative guiding principles for devising "hot-carrier resistant" device structures.     

A hot-carrier analysis of submicrometer MOSFET's

Based on Monte Carlo (MC) device simulations, an analysis of hot-carrier effects in submicrometer n-MOSFETs is presented that provides detailed insight because the high-energy electrons are treated directly. The DC stress characteristics of both lightly-doped drain (LDD) and conventional As source/drain devices are found to correlate with the surface hot-electron concentration, and agreement with experimental data shows that the electron flux above 3 eV, integrated along the channel, can be used to predict device degradation. The simulations indicate that the whole DC stress characteristic can be attributed to hot electrons, while the holes generated by impact ionization have a very small probability of gaining enough energy to be injected over the oxide barrier     

A new DC Drain-Current-Conductance method (DCCM) for thecharacterization of effective mobility (μeff) and seriesresistances (Rs, Rd) of fresh and hot-carrierstressed graded junction MOSFETs

A simple new DC technique is developed to extract the gate bias dependent effective channel mobility (u_eff) and series resistances (R_s and R_d) of graded junction n- and p-channel MOSFETs. This technique is found to be accurate and effective for devices with differing channel lengths and also for devices after nonuniform hot-carrier degradation. The parameter values extracted provide further insight into the damage mechanisms of hot-carrier stressed graded junction nMOSFETs and are usable in circuit and reliability simulation. This technique is especially useful for the optimization of hot-carrier resistant structures of submicrometer MOSFETs     

About long-term effects of hot-carrier stress on n-MOSFETS

Transistor characteristics and charge-pumping results obtained during nonuniform long-term hot-carrier stress on n-MOSFETs (no LDD) will be presented. Apart from identifying the overall degradation processes and their drift dynamics, this work focuses on the dependence of the device damage on different stress conditions which are representative for typical applications in the large field of analogue and digital automotive electronic circuits.     

Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In this regime, electrons can gain sufficient kinetic energy necessary to create interface states, hence inducing device degradation. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gate-bias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device.     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.