Transparent Oxide Thin-Film Transistors Composed of Al and Sn-doped Zinc Indium Oxide

We have fabricated the transparent bottom gate thin-film transistors (TFTs) using Al and Sn-doped zinc indium oxide (AT-ZIO) as an active layer. The AT-ZIO active layer was deposited by RF magnetron sputtering at room temperature, and the AT-ZIO TFT showed a field effect mobility of 15.6 $ hbox{cm}^{2}/hbox{Vs}$ even before annealing. The mobility increased with increasing the $hbox{In}_{2}hbox{O}_{3}$ content and postannealing temperature up to 250 $^{circ}hbox{C}$. The AT-ZIO TFT exhibited a field effect mobility of 30.2 $hbox{cm}^{2}/hbox{Vs}$, a subthreshold swing of 0.17 V/dec, and an on/off current ratio of more than $10^{9}$ .      

Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: nor Gate Application

We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20-nm-thick $hbox{Al}_{2}hbox{O}_{3}$ for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at 200 $^{ circ}hbox{C}$. As characterized with single gate (SG), DG, and ground plane (GP) modes, our ZnO TFTs are well operated under 5 V. DG-mode TFT showed a field mobility of 0.38 $ hbox{cm}^{2}/hbox{V} cdot hbox{s}$, a high saturation current of 6 $muhbox{A}$, and an on/off current ratio of $sim hbox{10}^{6}$, while SG- and GP-mode TFTs showed a similar value of mobility but with lower current. Using DG and GP modes, nor gate operation was well demonstrated.      

RF Power Measurements of InAlN/GaN Unstrained HEMTs on SiC Substrates at 10 GHz

Unstrained high-electron mobility transistors (HEMTs) were fabricated from InAlN/GaN on semi-insulating SiC substrates. The devices had 0.24-$muhbox{m}$ T-gates with a total width of $hbox{2} times hbox{150} muhbox{m}$. Final passivated performance values for these devices are $I_{max} = hbox{1279} hbox{mA/mm}$, $I_{rm DSS} = hbox{1182} hbox{mA/mm}$ , $R_{c} = hbox{0.43} Omega cdot hbox{mm}$, $rho_{s} = hbox{315} Omega/hbox{sq}$, $f_{T} = hbox{45} hbox{GHz}$, $f_{max({rm MAG})} = hbox{64} hbox{GHz}$, and $g_{m} = hbox{268} hbox{mS/mm}$. Continuous-wave power measurements at 10 GHz produced $P_{rm sat} = hbox{3.8} hbox{W/mm}$, $G_{t} = hbox{8.6} hbox{dB}$, and $hbox{PAE} = hbox{30}%$ at $V_{rm DS} = hbox{20} hbox{V}$ at 25% $I_{rm DSS}$ . To our knowledge, these are the first power measurements reported at 10 GHz for this material.      

Improvement of Interpoly Dielectric Characteristics by Plasma Nitridation and Oxidation for Future nand Flash Memory

In this letter, plasma nitridation and oxidation on interpoly dielectric (IPD; $hbox{SiO}_{2}hbox{-}hbox{SiN}hbox{-}hbox{SiO}_{2}$ ) for cell programming speed and reliabilities are investigated. Nitrided top oxide with $hbox{N}_{2}$ plasma shows excellent physical and electrical properties in terms of edge profile on IPD and fast programming voltage. However, plasma nitridation on a floating gate suffers from data retention problems that result from nitridelike residue along the word line. A method to densify and reoxidize bottom oxide with $hbox{O}_{2}$ plasma oxidation is proposed for leakage path inhibition and data retention improvement.      

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.      

The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves $> ,$18 dB conversion gain, a flat noise figure $≪, $5.5 dB from 500 MHz to 7 GHz, IIP2$ ={+}$20 dBm and IIP3 $={-}$3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than ${hbox{0.01~mm}}^{2}$ in 65 nm CMOS.      

High-Program/Erase-Speed SONOS With In Situ Silicon Nanocrystals

In this letter, for the first time, we have successfully fabricated silicon-oxide-nitride-oxide-silicon (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method. This process is simple and compatible to modern IC processes. Different Si-NCs deposition times by in situ method were investigated at first. SONOS devices with embedded Si-NCs in silicon nitride exhibit excellent characteristics in terms of larger memory windows (> 5.5 V), lower operation voltage, high P/E speed, and longer retention time (> 10⁸ s for 13% charge loss).     

A High-Throughput Maximum a Posteriori Probability Detector

This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo processing, can approach performance close to the channel capacity limit. The implementation benefits from optimizations performed at both algorithm and circuit level. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 Mb/s while consuming 2.4 W. The 16-state EEPR4 channel detector is implemented in a 0.13$ mu{hbox {m}}$ CMOS technology and has a core area of 7.1 ${hbox {mm}}^{2}$.      

On-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage

The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.     

Low-Voltage Organic Field-Effect Transistor With PMMA/$ hbox{ZrO}_{2}$ Bilayer Dielectric

This paper reports on the application of a bilayer polymethylmethacrylate (PMMA)/ $hbox{ZrO}_{2}$ dielectric in copper phthalocyanine (CuPc) organic field-effect transistors (OFETs). By depositing a PMMA layer on $hbox{ZrO}_{2}$, the leakage of the dielectric is reduced by one order of magnitude compared to single-layer $hbox{ZrO}_{2}$. A high-quality interface is obtained between the organic semiconductor and the combined insulators. By integrating the advantages of polymer and high- $k$ dielectrics, the device achieves both high mobility and low threshold voltage. The typical field-effect mobility, threshold voltage, on/off current ratio, and subthreshold slope of OFETs with bilayer dielectric are $hbox{5.6}timeshbox{10}^{-2} hbox{cm}^{2}/hbox{V} cdot hbox{s}$, 0.8 V, $hbox{1.2} times hbox{10}^{3}$, and 2.1 V/dec, respectively. By using the bilayer dielectrics, the hysteresis observed in the devices with single-layer $hbox{ZrO}_{2}$ is no longer present.      

Simultaneous All-Optical and and nor Gates for NRZ Differential Phase-Shift-Keying Signals

A scheme for realizing all-optical logic AND and NOR gates simultaneously for nonreturn-to-zero differential phase-shift-keying signals is proposed and demonstrated based on a delayed interferometer and two semiconductor optical amplifiers. Experimental demonstration at 20 Gb/s verifies the logic integrity of this scheme. The final results are derived in the ON-OFF keying format with clear open eyes and extinction ratios over 10 dB. The proposed scheme can be expanded to realize arbitrary logic gate.     

On the Capacity of Ad Hoc Networks Under Random Packet Losses

We consider the problem of determining asymptotic bounds on the capacity of a random ad hoc network. Previous approaches assumed a link layer model in which if a transmitter-receiver pair can communicate with each other, i.e., the signal to interference and noise ratio (SINR) is above a certain threshold, then the transmitted packet is received error-free by the receiver thereby. Using this model, the per node capacity of the network was shown to be $Theta left ( {{ 1}over { sqrt {nlog {n}}}}right )$. In reality, for any finite link SINR, there is a nonzero probability of erroneous reception of the packet. We show that in a large network, as the packet travels an asymptotically large number of hops from source to destination, the cumulative impact of packet losses over intermediate links results in a per-node throughput of only $Oleft ( {{ 1}over { n}}right )$ under the previously proposed routing and scheduling strategy. We then propose a new scheduling scheme to counter this effect. The proposed scheme provides tight guarantees on end-to-end packet loss probability, and improves the per-node throughput to $Omega left ( {{ 1}over { sqrt {n} left ({log {n}}right )^{{ alpha {+2}}over { 2(alpha -2)}}}}right )$ where $alpha >2$ is the path loss exponent.      

Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices

The physical model for field enhancement (FE) and the edge effects of body-tied FinFET charge-trapping NAND Flash devices are extensively studied in this paper. First, analytical equations are derived to provide insight to the FE effect for FinFET devices, and these analytical results are validated by 3-D TCAD simulation and experimental verification. Next, complicated programming and erasing characteristics and transconductance and subthreshold slope $(g_{m}/SS)$ behaviors are completely explained by the nonuniform injection behavior along various corner edges in FinFET. FE allows high program and erase speed and larger memory window. On the other hand, the edge effect complicates the device DC $I$– $V$, as well as programming and erasing characteristics, and these must be taken into account in memory circuit design.      

Proposal for All-Optical Switchable or/xor Logic Gates Using Sum-Frequency Generation

All-optical logic gate based on parametric processes in periodically poled lithium niobate (PPLN) waveguides is a promising technique in future high-speed all-optical signal processing. A simple realization of switchable or/xor logic gates at 40 Gb/s is proposed and numerically demonstrated using sum-frequency generation in a PPLN waveguide. By appropriately adjusting the input signal power and choosing the waveguide length, or and xor logic gates can be obtained. The operation performance is simulated, including eye diagrams and Q-factor. The input signal powers and waveguide length are optimized, providing a theoretical basis for achieving the optimal performance for the switchable or/xor logic gates     

Large-Scale In Situ Fabrication of Voltage-Programmable Dual-Layer High-$kappa$ Dielectric Carbon Nanotube Memory Devices With High On/Off Ratio

In this letter, we report on measurements of carbon nanotube (CNT) field-effect transistors with high on/off ratio to be used as nonvolatile memory cells operating at room temperature. Thousands of memory devices have been realized using a complete in situ fabrication method. The self-aligned fabrication process allows large-scale production of CNT memory devices with high yield. The memory function is obtained by the threshold voltage shift due to the highly reproducible hysteresis in the transfer characteristics. The ratio of the current levels between a logical “1” and a “0” is about $hbox{10}^{6}$.      

An on–off-Keying Optical Receiver With Dual Thresholds and Erasure Zone

An ON-OFF-keying optical receiver with dual thresholds and an erasure zone is proposed. This configuration can be applied to track the optimized decision level adaptively and obtain additional coding gain from forward-error correction without increasing the code rate. Our analysis shows that in both unamplified and optically preamplified receivers, the required Q value for the bit-error rate of 10^-12 can be reduced by 1.8 dB, if errors arise in burst nature and the optimized erasure zone width is around 7%-11% of the signal swing.     

Low Phase Noise Self-Switched Biasing CMOS LC Quadrature VCO

A self-switched biasing quadrature voltage-controlled oscillator (VCO) is presented. It is implemented by directly injecting the oscillation signal of one VCO core into the other VCO core through the divided tail current sources without additional active devices for coupling. The proposed coupling structure automatically switches the NMOS field-effect transistors used in VCO cores and current sources from strong inversion to accumulation. Since the deep switching of MOSFETs was reported to physically reduce flicker noise, the proposed quadrature VCO (QVCO) is expected to improve the phase noise performance, which is confirmed experimentally. The designed QVCO using 0.18- $mu{hbox{m}}$ CMOS technology operates from 1.86 to 2.2 GHz with a 17% frequency tuning range. The measured phase noise is from $-$ 129.1 to $-$ 134.5 dBc/Hz at a 1-MHz offset, which is really close to ideal simulation results with the NMOS model disabling the flicker noise components. The average measured phase noise is 7.2 dB below the simulated one with a flicker noise model, which verifies the physical reduction of flicker noise by deep switching of the MOSFET. The phase noise figure-of-merit ranges from 179 to 185 over the entire tuning range. The QVCO dissipates 20 mA from a 1.8-V supply.      

PPLN-Based Flexible Optical Logic and Gate

All-optical flexible 20-Gb/s logic and gate based on cascaded sum- and difference-frequency generation in a periodically poled lithium niobate waveguide is proposed and experimentally demonstrated. The theoretical analyses further indicate that 40-, 80-, and 160-Gb/s ultrahigh-speed logic and operations can potentially be performed. Moreover, it is expected that the and output can be tuned in a wide wavelength range (67 nm) with slight fluctuation of the Q-factor and extinction ratio.     

Effect of Dielectric Thickness on Power Performance of AlGaN/GaN HEMTs

The effect of $hbox{SiN}_{x}$ passivation thickness on the power performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) has been studied. A model is proposed to explain the surface-state dispersion and passivation of AlGaN/GaN HEMTs. Based on this model, a multidielectic passivation method has been proposed and demonstrated to both provide lower dielectric capacitance and help remove dc–RF dispersion.