A tactless analog-to-digital converter with bit-by-bit equilibration

The structure and general properties of a tactless analog–digital converter (ADC) with bit-by-bit equilibration combining in itself the characters both of a parallel ADC and an ADC with bit-by-bit equilibration and occupying on operation speed an intermediate position between the aforementioned classes of ADCs is considered. The converter is an asynchronous relay-pulse system, in which conversion of an analog signal into digital code is carried out naturally (“self-flowing”) and the conversion speed of which is determined only by delays of units that are included in its structure. The basic calculated relations illustrating a principle of operation of the tactless ADC are given. Results of simulation of a tactless ADC in the MatLab + Simulink software environment and its dynamic performances are presented.     

一种新的基于旋转变压器的测速方法

提出一种旋转变压器输出信号的软件解调方法,即不使用RDC(resolve to digital converter)芯片转换,而是直接将旋转变压器输出的模拟信号连接到DSP (TMS320F2812)的模拟一数字转换(ADC,analog to digital converter)模块上,通过软件算法对旋转变压器的输出...     

混合信号系统表征及行为建模——背景、基本理论、测量方案和关键技术

软件无线电(SDR)的发展推动了无线通信系统的高度集成化。该类系统包含射频、模/数或数/模转换(ADC和DAC)和高速系统时钟信号电路,故称为混合信号系统。目前对其表征和行为建模方法还处于探索阶段。综合论述了SDR混合信号系统表征和行为建模的研究现状,重点描述基于X参数的混合信号系统表征与建模的基本理论、测量方案和关键技术,给出了混合信号系统用X参数表征的模型,使X参数拓展到模拟和数字混合域。最后,对于混合信号系统建模方法的研究趋势进行了分析与预测。     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

电力监控器硬件电路设计

电力控制器以87C196CB单片机为控制核心,数字信号处理芯片ADSP-2185执行数据采集和处理功能.作为主控制器的单片机具有内置的CAN总线接口,使远程通信更容易实现.数据采集采用AD73360模/数转换器芯片,它是一个6通道16位同步模拟输入转换器,与DSP结合实现了对多路电压、电流信号的实时采集与数据处理.     

VGA转DVI信号转换器的设计

随着以LCD和其他数字平板显示技术的飞速发展,数字视频接口逐渐地被人们广泛应用。本文选择Intersil公司的ISL98003作为模数转换芯片,采用单片机uPSD3234控制,完成了模拟转数字视频信号转换器的设计。模数转换器内置ADC及PLL电路,将模拟的视频信号转化成数字信号,并针对CRT显示的值进行校正,得到适合LCD象素特性的灰度信号。     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

时间交替采样系统的误差测量与FPGA实现

时间交替采样结构是模数转换中提高采样率的1种有效方法.但由于器件工艺限制,每个通道的不一致性会引入通道失配误差,而这些误差会导致信号存在较大的杂散分量,将会严重影响ADC的性能.通道误差包括增益误差、时间误差、偏置误差.提出了一种频域的方法通过对单路采样信号做快速傅里叶变换并由固定位置方法找出误差的频域值,对此频域值做...     

VLBI wideband digital SSB converter based on poly-phase filter banks

With the further development in astronomy and deep space exploration, the incremental improvements to be expected in the very long baseline interferometry (VLBI) is real-time, high sensitivity, high reliability and wider frequency coverage. The VLBI data acquisition backend plays an important role in the VLBI station. Recently, based on advances in digital hardware like analog-to-digital conversion, digital signal processing, field programmable gate arrays (FPGA) and so on, it has become practical to sample and digitally process the intermediate frequency signal directly. Digital base-band converters (DBBC) will replace analog base-band converters (ABBC) in the VLBI data acquisition backend. This paper presents a sequence of simple modifications to sampled data structures based on the analog prototype system to obtain the basic poly-phase structure in a VLBI data acquisition backend. The theoretical principles of a digital SSB down converter are discussed in detail. The approach adopts multi-rate signal processing for the designed filters in a digital SSB down converter which is carried out by virtex-4 FPGA chips. The observation result shows this model of DBBC is of better performances than ABBC.     

AD7606在测井采集模块中的应用与设计

鉴于模数转换器在测井采集模块中的重要性,提出了一种以XC3S500E芯片为控制核心和多通道模数转换器相结合的低速模拟信号采集设计方案,给出了硬件结构框图。着重介绍了16位、8通道模数转换芯片AD7606的工作原理及常用工作方式设置,分析了其在采集模块中的功能及作用。测井信号的实时采集处理需要通过软件编程完成,以磁记号为例介绍了低速模拟信号采集和处理的过程。通过两年的现场使用表明,该设计方案采用的信号处理方法能够很好地完成相应模拟信号的处理,并取得了良好应用效果。     

Design considerations for low power time‐mode SAR ADC

This paper describes circuit design considerations for realization of low power dissipation successive approximation register (SAR) analog‐to‐digital converter (ADC) with a time‐mode comparator. A number of design issues related to time‐mode SAR ADC are discussed. Also, noise and offset models describing the impact of the noise and offset on the timing error of time‐domain comparator are presented. The results are verified by comparison to simulations. The design considerations mentioned in this paper are useful for the initial design and the improvements of time‐mode SAR ADC. Then, a number of practical design aspects are illustrated with discussion of an experimental 12‐bit SAR ADC that incorporates a highly dynamic voltage‐to‐time converter and a symmetrical input time‐to‐digital converter. Prototyped in a 0.18‐µm six‐metal one‐polysilicon Complementary Metal‐Oxide‐Semiconductor (CMOS) process, the ADC, at 12 bit, 500 kS/s, achieves a Nyquist signal‐to‐noise‐and‐distortion ratio of 53.24 dB (8.55 effective number of bits) and a spurious‐free dynamic range of 70.73 dB, while dissipating 27.17 μW from a 1.3‐V supply, giving a figure of merit of 145 fJ/conversion‐step. Copyright © 2013 John Wiley & Sons, Ltd.     

FFT‐based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform (FFT)‐based digital calibration method for 1.5 bit/stage pipeline analog‐to‐digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non‐ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low‐gain OPAMP can be used in high‐performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal‐to‐noise‐and‐distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley & Sons, Ltd.     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.     

A versatile data transmission training module

A versatile user-interactive data transmission training system, comprising a transmitter and a receiver section, is presented. The transmitter and the receiver can be used as separate units or can be coupled to form a complete system. There are four multiplexed analog inputs. The digital equivalent of these analog data are transmitted over a single wire. Digital data, counter states, and shifting processes are indicated by light-emitting diodes (LEDs). Analog input signals can be DC or AC. The transmission sequence can either be manually effected by the experimenter using momentary switches or can be operated automatically. The advantage of this design is that the operations of the various units, e.g. analog-to-digital converter (ADC), digital-to-analog converter (DAC), multiplexer, counters, etc., can be separately studied. In addition, the experiments can (by manual operation) monitor the sequence of events progressively, via LEDs, thereby providing a better understanding of the individual units     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

基于PCI总线DSP数据采集系统设计

文中提出基于PCI局部总线DSP通用数据采集系统设计方案,该方案采用TMS320VC5416作为外围核心处理单元,PCI2040作为PCI桥芯片,TLV1572作为数据转换器通过软件开发实现数据采集,具有高速度,低成本的优点.给出PCI接口硬件设计方法及关键点,介绍基于Windows2000操作系统的WDM驱动程序的结构及原理,驱动程序的基本功能的实现方法及应用程序与驱动程序的通信技术,介绍了实现DSP自启动的方式.     

MASH结构ADC中的自适应校正系统设计

随着大规模集成电路的快速发展,Delta-Sigma（∑-△）模数转换技术因为它的良好性能和易集成的优势,越来越受到广泛的关注和应用。本文针对实际电路相对于理想设计的性能下降来分析其原因。同时针对主要来自模拟电路的诸如实际电容的不精确匹配、放大器的有限增益等因素,通过MATLAB模型来详细分析这些模拟电路误差会对于电路性能产生的影响。本文同时提出了一种自适应校正系统,通过将LMS自适应算法应用于ADC电路,来获得对模拟电路误差的校正。并通过MATLAB分析获得理想状态、无校正系统和校正系统的性能比较来体现校正系统的实际应用价值。     

A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI

Multiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high-performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a V/I converter, an ac/dc converter, an AM radio receiver, a digitally controlled analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation; results show that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed digital circuit design at the gate level.     

电容式心电测量装置的设计

针对传统心电图测量中的不足,设计了利用电容耦合方式测量心电信号的测试系统。以电容传感器拾取极微弱的心电信号,经过缓冲、滤波、放大等环节,使其达到模数转换器测量要求。测量数据经单片机处理后再通过RS-232传送至计算机,由计算机进行信号恢复、数据存储和分析。测试结果表明了该方法的可行性,具有广泛的应用前景。     

Self‐calibrated SAR ADC based on split capacitor DAC without the use of fractional‐value capacitor

A successive approximation register analog‐to‐digital converter (SAR ADC) based on a split‐capacitor digital‐to‐analog converter (CDAC) with a split binary weighted capacitor array and C‐2C ladder is proposed. In present design, a unit split capacitor is used in the CDAC instead of the fractional‐value capacitor in the conventional configuration. The preset error induced by the unit split capacitor and the mismatch error of the upper bit CDAC are self‐calibrated. The calibration range and the impact of calibration DAC resolution on circuit linearity are studied to provide an optimum design guideline. Behavior simulation and post‐layout simulation are performed to verify the proposed calibration method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.