Optimization of AuGe-Ni-Au ohmic contacts for GaAs MOSFETs

GaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are promising devices for high-speed and high-power applications. One important factor influencing the performance of a GaAs MOSFET is the characteristics of ohmic contacts at the drain and source terminals. In this paper, AuGe-Ni-Au metal contacts fabricated on a thin (930 /spl Aring/) and lightly doped (4/spl times/10/sup 17/ cm/sup -3/) n-type GaAs MOSFET channel layer were studied. The effects of controllable processing factors such as the AuGe thickness, the Ni/AuGe thickness ratio, alloy temperature, and alloy time to the characteristics of the ohmic contacts were analyzed. Contact qualities including specific contact resistance, contact uniformity, and surface morphology were optimized by controlling these processing factors. Using the optimized process conditions, a specific contact resistance of 5.6/spl times/10/sup -6/ /spl Omega//spl middot/cm/sup 2/ was achieved. The deviation of contact resistance and surface roughness were improved to 1.5% and 84 /spl Aring/, respectively. Using the improved ohmic contacts, high-performance GaAs MOSFETs (2 /spl mu/m/spl times/100 /spl mu/m) with a large drain current density (350 mA/mm) and a high transconductance (90 mS/mm) were fabricated.     

Thermally stable Ge/Ag/Ni Ohmic contact for InAlAs/InGaAs/InP HEMTs

Excellent annealed ohmic contacts based on Ge/Ag/Ni metallization have been realized in a temperature range between 385 and 500/spl deg/C, with a minimum contact resistance of 0.06 /spl Omega//spl middot/mm and a specific contact resistivity of 2.62 /spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ obtained at an annealing temperature of 425/spl deg/C for 60 s in a rapid thermal annealing (RTA) system. Thermal storage tests at temperatures of 215 and 250/spl deg/C in a nitrogen ambient showed that the Ge/Ag/Ni based ohmic contacts with an overlay of Ti/Pt/Au had far superior thermal stabilities than the conventional annealed AuGe/Ni ohmic contacts for InAlAs/InGaAs high electron mobility transistors (HEMTs). During the storage test at 215/spl deg/C, the ohmic contacts showed no degradation after 200 h. At 250/spl deg/C, the contact resistance value of the Ge/Ag/Ni ohmic contact increased only to a value of 0.1 /spl Omega//spl middot/mm over a 250-h period. Depletion-mode HEMTs (D-HEMTs) with a gate length of 0.2 /spl mu/m fabricated using Ge/Ag/Ni ohmic contacts with an overlay of Ti/Pt/Au demonstrated excellent dc and RF characteristics.     

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.     

Ion implanted AlGaN-GaN HEMTs with nonalloyed Ohmic contacts

In this letter, the incorporation of Si implantation into AlGaN-GaN high-electron mobility transistor (HEMT) processing has been demonstrated. An ultrahigh-temperature (1500/spl deg/C) rapid thermal annealing technique was developed for the activation of Si dopants implanted in the source and drain. In comparison to control devices processed by conventional fabrication, the implanted device with nonalloyed ohmic contact showed comparable device performance with a contact resistance of 0.4 /spl Omega//spl middot/mm, I/sub max/ of 730 mA/mm, f/sub t//f/sub max/ of 26/62 GHz, and a power of 3.4 W/mm on sapphire. These early results demonstrate the feasibility of implantation incorporation into GaN-based device processing as well as the potential to increase yield, reproducibility, and reliability in AlGaN-GaN HEMTs.     

Improvement of the luminous intensity of light-emitting diodes by using highly transparent Ag-indium tin oxide p-type ohmic contacts

We have investigated Ag-indium tin oxide (ITO) scheme for obtaining high-quality p-type ohmic contacts for GaN-based light-emitting diodes (LEDs). The Ag(1 nm)-ITO(200 nm) contacts exhibit greatly improved electrical characteristics when annealed at temperatures in the range 400/spl deg/C-600/spl deg/C for 1 min in air, yielding specific contact resistances of /spl sim/10/sup -4/ /spl Omega//spl middot/cm/sup 2/. In addition, the contacts give transmittance of about 96% at 460 nm, which is far better than that of the conventionally used oxidized Ni-Au contacts. It is shown that the luminous intensity of blue LEDs fabricated with the Ag-ITO contacts is about three times higher than that of LEDs with oxidized Ni-Au contacts. This result strongly indicates that the Ag-ITO scheme can serve as a highly promising p-type ohmic contact for the realization of high brightness near ultraviolet LEDs.     

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.     

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.     

High-reflectivity Al-Pt nanostructured Ohmic contact to p-GaN

The effect of nanoscale Pt islands on the electrical characteristics of contacts to p-type gallium nitride (GaN) has been investigated to explore the feasibility for the flip-chip configuration light-emitting diodes (LEDs) using an Al-based reflector. An as-deposited Al contact to p-GaN with a net hole concentration of 3/spl times/10/sup 17/cm/sup -3/ was rectifying. However, an Al contact with nanoscale Pt islands at the interface exhibited ohmic behavior. A specific contact resistivity of 2.1/spl times/10/sup -3//spl Omega//spl middot/cm/sup 2/ and a reflectance of 84% at 460 nm were measured for the Al contact with nanoscale Pt islands. Current-voltage temperature measurements revealed a Schottky barrier height reduction from 0.80 eV for the Al contact to 0.58 eV for the Al contact with nanoscale Pt islands. The barrier height reduction may be attributed to electric field enhancement and the enhanced tunneling due to the presence of the nanoscale Pt islands. This will offer an additional silver-free option for the p-type ohmic contact in flip-chip configuration LEDs. Theory suggests that the ohmic contact characteristics may be improved further with smaller Pt islands that will enhance tunneling across the interface with the GaN and in the vicinity of the Pt-Al interface.     

Photosensitive Polymer Thin-Film FETs Based on Poly(3-octylthiophene)

The effects of white light on the electrical performance of polymer thin-film transistors (PTFTs) based on regioregular poly(3-octylthiophene) (P3OT) are investigated. Upon illumination, a significant increase in the PFET's drain current is observed with a maximum photosensitivity of 10/sup 4/ in the subthreshold operation and a broad-band responsivity with a maximum value of 160 mA/W at irradiance of 1.7 mW/cm/sup 2/ and at low gate biases. The photosensitivity decreases with the increase in the absolute gate bias. The simultaneous control of the device with both the gate voltage and illumination is possible at low irradiances of <0.7 mW/cm/sup 2/. It is found that the illumination effectively decreases the threshold voltage of the device, but it does not change the field-effect mobility. Using a trap model, it is shown that the narrow layers close to the drain and source contacts with high concentrations of defects are two possible regions for photogeneration of excitons and separation of charges. Using the theory of space-charge limited conduction, the extracted band mobility for P3OT is 0.08 cm/sup 2//V/spl middot/s, while a mobility of 8/spl times/10/sup -5/cm/sup 2//V/spl middot/s is found for the regions next to the source and drain contacts. The PTFT's high photosensitivity at zero gate voltage suggests a simple design of low-voltage, high-sensitivity two-terminal photodetectors for applications in large-area flexible optoelectronics.     

Submicron AlGaN/GaN HEMTs with very high drain current density grown by plasma-assisted MBE on 6H-SiC

High electron mobility transistors (HEMTs) were fabricated from AlGaN/-GaN layers grown by plasma-assisted molecular beam epitaxy on semi-insulating 6H-SiC substrates. Room-temperature Hall effect measurements yielded a polarization-induced 2DEG sheet charge of 1.3/spl middot/10/sup 13/ cm/sup -2/ and a low-field mobility of 1300 cm/sup 2//V/spl middot/s. Submicron gates were defined with electron beam lithography using an optimized two-layer resist scheme. HEMT devices repeatedly yielded drain current densities up to 1798 mA/mm, and a maximum transconductance of 193 mS/mm. This is the highest drain current density in any AlGaN-GaN HEMT structure delivering significant microwave power reported thus far. Small-signal testing of 50-/spl mu/m wide devices revealed a current gain cutoff frequency f/sub T/ of 52 GHz, and a maximum frequency of oscillation f/sub max/ of 109 GHz. Output power densities of 5 W/mm at 2 GHz, and 4.9 W/mm at 7 GHz were recorded from 200-/spl mu/m wide unpassivated HEMTs with a load-pull setup under optimum matching conditions in class A device operation.     

Low resistance and reflective Mg-doped indium oxide-Ag ohmic contacts for flip-chip light-emitting diodes

We have investigated an Mg-doped In/sub x/O/sub y/(MIO)-Ag scheme for the formation of high-quality ohmic contacts to p-type GaN for flip-chip light-emitting diodes (LEDs). The as-deposited sample shows nonlinear current-voltage (I--V) characteristics. However, annealing the contacts at temperatures of 330/spl deg/C-530/spl deg/C for 1 min in air ambient results in linear I--V behaviors, producing specific contact resistances of 10/sup -4/--10/sup -5/ /spl Omega//spl middot/cm/sup 2/. In addition, blue LEDs fabricated with the MIO-Ag contact layers give forward-bias voltages of 3.13-3.15 V at an injection current of 20 mA. It is further shown that LEDs made with the MIO-Ag contact layers give higher output power compared with that with the Ag contact layer. This result strongly indicates that the MIO-Ag can be a promising scheme for the realization of high brightness LEDs for solid-state lighting application.     

High-performance double-recessed enhancement-mode metamorphic HEMTs on 4-in GaAs substrates

Enhancement-mode InAlAs/InGaAs/GaAs metamorphic HEMTs with a composite InGaAs channel and double-recessed 0.15-/spl mu/m gate length are presented. Epilayers with a room-temperature mobility of 10 000 cm/sup 2//V-s and a sheet charge of 3.5/spl times/10/sup 12/cm/sup -2/ are grown using molecular beam epitaxy on 4-in GaAs substrates. Fully selective double-recess and buried Pt-gate processes are employed to realize uniform and true enhancement-mode operation. Excellent dc and RF characteristics are achieved with threshold voltage, maximum drain current, extrinsic transconductance, and cutoff frequency of 0.3 V, 500 mA/mm, 850 mS/mm, and 128 GHz, respectively, as measured on 100-/spl mu/m gate width devices. The load pull measurements of 300-/spl mu/m gate width devices at 35 GHz yielded a 1-dB compression point output power density of 580 mW/mm, gain of 7.2 dB, and a power-added efficiency of 44% at 5 V of drain bias.     

All-refractory GaAs FET using amorphous TiWSixsource/drain metallization and graded-InxGa1-xAslayers

We report on the fabrication of an all-refractory GaAs field-effect transistor having non-alloyed source and drain ohmic contacts and a TiW/Au refractory gate metallization. The ohmic contacts consist of amorphous TiWSi_x metallization and intervening graded InGaAs layers grown by low pressure organometallic vapor phase epitaxy (LPOMVPE). The amorphous TiWSi_x, is formed using alternating layers of TiW(10 Å) and Si(1.5 Å) deposited by an RF magnetron sputtering technique. The resulting all-refractory FET devices exhibited excellent dc transistor characteristics with measured transconductance of 140 mS/mm. The dc performance of these devices was comparable to conventional devices with AuGe/Ni/Au contacts fabricated using similar material structures     

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup $/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Ga2O3(Gd2O3)/InGaAsenhancement-mode n-channel MOSFETs

We have demonstrated the first Ga₂O₃(Gd₂O₃) insulated gate n-channel enhancement-mode In_0.53Ga_0.47As MOSFET's on InP semi-insulating substrate. Ga₂O₃(Gd₂ O₃) was electron beam deposited from a high purity single crystal Ga₅Gd₃O₁₂ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-μm gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f_t, and the maximum frequency of oscillation, f_max, of 7 and 10 GHz were obtained, respectively, for a 0.75×100 μm² gate dimension device at a gate voltage of 3 V and drain voltage of 2 V     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

Indium tin oxide transparent electrodes for broad-area top-emitting vertical-cavity lasers fabricated using a single lithography step

We report for the first time top-emitting buried oxide vertical cavity lasers using transparent indium tin oxide electrodes. Our process enables broad-area InAlGaAs VCSELs to be fabricated in a single lithography step, thus allowing the fast turn-around time necessary for evaluating VCSEL epitaxial materials. The ITO contacts attain a peak transmission of 96%, a specific contact resistance of 10/sup -5/ /spl Omega//spl middot/cm/sup 2/, and a sheet resistivity of 2.5/spl times/10/sup -4/ /spl Omega//spl middot/cm. Under room temperature CW pumping, the devices exhibit a minimum threshold current density of 1.2 kA/cm/sup 2/ at a wavelength of 801 mm, and have a maximum light output power of 5.2 mW.     

Low loss, thin p-clad 980-nm InGaAs semiconductor laser diodes with an asymmetric structure design

Thin p-clad InGaAs ridge waveguide quantum-well lasers having an asymmetric structure design were fabricated. The internal absorption coefficient is as low as 2.5 cm/sup -1/, due to the restricted field extension in the 0.3-/spl mu/m-thick p-type top AlGaAs cladding layer. Ti-Pt-Au metallization is used outside the ridge to provide adherence on the oxide while Au directly contacts the ridge region. It is shown that the most likely source of loss in these thin p-clad devices is scattering at the rough interface between Au and the p/sup ++/ top GaAs layer, after ohmic contact heat treatment.