A bipolar mechanism for alpha-particle-induced soft errors in GaAsintegrated circuits

The alpha-particle-induced collected charge in undoped LEC semi-insulating GaAs is measured in n⁺-i-n⁺ and n ⁺-p-n⁺ isolation structures and is compared with the results of an analytical model based on a bipolar mechanism. In n ⁺-i-n⁺ isolation structures, a collected-storage multiplication phenomenon induced by alpha-particle incidence is observed. The measured collected charge is about three times the alpha-particle-generated charge. This phenomenon can be attributed to charge transfer between two adjacent n⁺ regions. The dominant charge-collection process continues for 2.4 ns in n⁺-i-n⁺ isolation structures, but in n⁺-p-n⁺ isolation structures, it stops within 0.8 ns. The measured collected charge decreases as the isolation gap and background acceptor concentration increase. These experimental results can be explained semiquantitatively by the analytical model. This suggests that the primary mechanism of soft errors in GaAs ICs is a bipolar mechanism     

Effects of a buried p-layer on alpha-particle immunity of MESFET's fabricated on semi-insulating GaAs substrates

Measurements of alpha-particle-induced charge are carried out for the first time on both conventional MESFET's fabricated directly on semi-insulating GaAs substrates and MESFET's with a buried p-layer. The maximum collected charge is found to be 65 fC in the MESFET's with a buried p-layer, one order smaller than in conventional MESFET's.     

Electron beam induced current imaging of near-contact regions insemi-insulating GaAs

Electron beam induced current (EBIC) in a scanning electron microscope has been used to image the internal electric field regions near implanted contacts on semi-insulating GaAs. Planar n⁺-i-p⁺ structures were fabricated with intercontact distances ranging from 5 to 100 μm. In cases where the diffusion length is short compared to the lengths of interest, the current collected is determined primarily by the local electric field profile. With no externally applied bias, we observe large current collection regions adjacent to the n⁺ contact, extending ~10-20 μm into the bulk material. Two-dimensional (2-D) imaging indicates that the regions are highly nonuniform. For small intercontact distances, the contact-related fields, which are produced by the diffusion and trapping of carriers from the contacts, can dominate the entire region. Changes in EBIC signal with the application of forward or reverse bias are used to monitor the interaction of the zero bias field and the applied field. This approach provides a good estimate of the field distributions in trap-dominated, high resistivity materials like semi-insulating GaAs, with a spatial resolution generally not obtained with other field imaging techniques     

Improvement of alpha-particle-induced soft-error immunity in a GaAsSRAM by a buried p-layer

Alpha-particle-induced soft-error immunity in a 1-kB GaAs SRAM was improved by a buried p-layer, which was formed in isolation regions as well as in FET regions and was designed to be completely depleted. The mean time between failures exceeded 10⁴ at an alpha-particle fluence of about 2.0×10⁴ cm^-2-s^-1 with a 1.0-μCi²⁴¹Am source. The alpha-particle energy had a peak at 4.0 MeV and was distributed from nearly 0 to 4.6 MeV. This value is five orders of magnitude better than that for a conventional SRAM without a buried p-layer. This improvement in the soft-error immunity can be achieved without increasing the access time or the power consumption by depleting the p-layer completely. Also discussed is the possibility of using a conductive p-layer scheme for higher integration of GaAs SRAMs     

Fabrication of 200-GHz fmax resonant-tunnelingdiodes for integration circuit and microwave applications

Room-temperature current densities of 1.3×10⁵ A/cm² and peak-to-valley ratios of 2.5 have been achieved for resonant tunneling diodes (RTDs) in the GaAs/AlAs material system. The devices were fabricated in a microwave-compatible process using topside contacts and a semi-insulating substrate to allow device integration. Proton implantation creates a nonconducting surface compatible with high-frequency coplanar transmission lines and other passive microwave structures     

GaAs integrated microwave circuits

GaAs has many desirable features that make it most useful for microwave and millimeter-wave integrated circuits. The process of selective epitaxial depositions of high purity single-crystal GaAs with various doping concentrations into semi-insulating GaAs substrates has been developed. These high-resistivity substrates (>10⁶ohm.cm) provide the electrical isolation between devices, eliminating the difficulties and deficiencies normally encountered in trying to obtain isolation with dielectrics, back-etching, p-n junctions, etc. This monolithic approach to integrated-circuits thus allows for improved microwave pedormance from the devices since parasitics are reduced to a minimum. Planar Gunn oscillators and Schottky barrier diodes have been fabricated for use in a completely monolithic integrated millimeter wave (94 GHz) receiving front end. The Gunn oscillators are made in a sandwich-type structure of three selective deposits whose carrier concentrations are approximately 10¹⁸-10¹⁵-10¹⁸cm^-3. The Schottky diodes consist of two deposits with concentrations of 10¹⁸and 10¹⁷cm^-3. The Schottky contact is formed by evaporating Mo-Au onto the 10¹⁷cm^-3deposits; all ohmic contacts are on the surface and are alloyed to the N⁺regions.     

Analytical solutions for the breakdown voltages of punched-through diodes having curved junction boundaries at the edges

Analytical expressions are derived for the breakdown voltages of punched-through diodes having a plane structure terminated with cylindrical and spherical curved boundaries at the edges, through the use of suitable approximations for the electric field in the depletion layer. The expressions derived include both p⁺-i-n⁺and p⁺-p-n⁺(or p⁺-n-n⁺) types and are given in terms of the middle-region (i-layer or p-layer) width, the radius of curvature of the junction edge, the punch-through voltage, and the plane parallel breakdown voltage of p⁺-i-n⁺diodes. The results obtained include a correlation between the middle-region (p-layer) width and the width of the depletion layer in the curved portions of the junction when the applied reverse bias across the diode is just sufficient so that punchthrough takes in the portions where the junction is plane parallel. These results are made use of in the breakdown voltage calculations.     

The transport and isolation properties of polycrystalline GaAs selectively grown by molecular beam epitaxy

Selective-area polycrystalline GaAs using SiO2masking is planarly grown by molecular beam epitaxy (MBE). The electric properties of the polycrystalline GaAs are investigated because this technology is very promising for device isolation in GaAs integrated circuit and electro-optic integration. Compared with the isolation characteristics of semi-insulating GaAs, polycrystalline GaAs has similar low-field resistivity, higher high-field leakage current, and no well-defined trap-fill-limited voltage. The grain boundary (GB) states of polycrystalline GaAs trap negative charge that builds up a potential barrier to hinder electron current. The GB density of states profile estimated from the IV characteristics shows a peak value 5 × 10¹²cm^-2.eV¹and a wide energy distribution, 0.33 eV above the equilibrium Fermi energy.     

High performance monolithic GaAlAs/GaAs photodiode arrays for voltage-controlled semiconductor switches

Monolithic GaAlAs/GaAs photodiode arrays (PDA's) have been developed as control elements for voltage-controlled switching applications. A p-type GaAs absorbing layer and an n-type GaAlAs window layer were grown by LPE on a semi-insulating GaAs substrate. Individual photodiodes were isolated and were series connected by an overlay metallization. A six cell PDA, having an active area of 1.28 mm², produces an open-circuit voltage of 5.3 V and a short-circuit current of 33 µA when subjected to a normally incident power flux of 50 mW/cm²at 865 nm. Such devices may be useful in a variety of voltage-controlled switching applications, opto-isolator circuits, and wherever low power, floating, voltage/bias sources are required.     

Two-dimensional numerical analysis of the minimum isolationdistance for GaAs digital large-scale integration

The minimum device isolation distance (L_min) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L_min is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L_min at room temperature is 1.3 μm with a bias voltage of 2 V and an acceptor concentration of 10¹⁵ cm^-3. L_min decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V     

A possible scaling limit for enhancement-mode GaAs MESFETs in DCFLcircuits

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×10¹² cm^-2·eV^-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8     

Effects of neutral buried p-layer on high-frequency performance ofGaAs MESFETs

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2×10¹² cm^-2 to 4×10¹² cm^-2, the maximum value of the cutoff frequency with a 0.2-μm gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2-μm-gate GaAs MESFETs     

Two-dimensional simulations of drain-current transients in GaAsMESFET's with semi-insulating substrates compensated by deep levels

Drain-current transients of GaAs MESFET's with deep donors “EL2” in the semi-insulating substrate are simulated in the range t=10^-13 to 10² s. It is shown that in the drain step responses, there exists a “quasi-steady state” where the deep donors do not respond to the voltage change and the drain currents become constant temporarily. The drain currents begin to decrease or increase gradually when the deep donors begin to capture or emit electrons, reaching real steady-state values. I-V curves are quite different between the “quasi-steady state” and the steady state. Therefore, the deep donors in the semi-insulating substrate can be causes of drain-current drifts and hysteresis in I-V curves. Effects of introducing a p-buffer layer are also studied. It is concluded that the use of a low acceptor density semi-insulating substrate combined with introducing a p-buffer layer is effective to minimize the unfavorable phenomena and to utilize high performances of GaAs MESFET's     

Improvement of GaAs MESFET performance using surface p-layer doping(SPD) technique

The development of a surface p-layer doping (SPD) technique to improve GaAs MESFET performance is presented. Very shallow p-type doping into the gate-drain and gate-source regions is used to improve the output conductance of the device. It is found that the threshold voltage is independent of the SPD dose. The transconductance degrades significantly as the p doping (Be, 10 keV) increases above 3×10 ¹²/cm². However, the output conductance and subthreshold current are improved with higher SPD dose. The gate-source reverse breakdown voltage is improved by about 90%, and the parasitic resistance increases by about 30% with an SPD of 5×10¹²/cm²     

A high-speed and highly uniform submicrometer-gate BPLDD GaAsMESFET for GaAs LSIs

The authors present formation conditions for ion-implanted regions of a GaAs buried p-layer lightly doped drain (BPLDD) MESFET that can improve short-channel effect, V_th uniformity, and FET operating speed, simultaneously. For 0.7-μm gates, a Mg⁺ dose of 2×10¹² cm^-2 at 300 keV and a Si⁺ dose of 2×10¹² cm^-2 at 50 keV are suitable for the p layer and n' layer, respectively. A σV _th of 7 mV is realized. Gate-edge capacitance of the 0.7-μm-gate BPLDD that consists of both overlap capacitance and fringing capacitance is successfully reduced to 0.5 fF/μm, which is about 50% of that of a non-LDD buried p-layer (BP) FET. Another parasitic capacitance due to the p-layer was found to have less effect on the speed than the gate-edge one. Consequently, the gate propagation delay time of the BPLDD can be reduced to 15 ps at power dissipation of 1 mW/gate, which is about 65% of that of a BP. Applying the 0.7-μm-gate BPLDD to 16-kb SRAMs, the authors have obtained a maximum access time of less than 5 ns with a galloping test pattern     

MOVPE-grown millimeter-wave InGaAs mixer diode technology andcharacteristics

The merits of InGaAs-based millimeter-wave mixer diodes are explored experimentally and theoretically. Schottky junctions on InGaAs exhibit barriers (φ_b) in the neighborhood of 0.25 eV. The high mobility of InGaAs contributes to the low n⁺ sheet resistances of 1.9-5 Ω/square for 1-μm n⁺ InGaAs layers (n_s=1.5×10¹⁹ cm^-3, μ _n=1800 cm²/V·s) grown with our in-house Metalorganic Vapor Phase Epitaxy (MOVPE) system, The design, material growth, fabrication, and characterization of InGaAs integrated mixer/antennae are reported. Pt plating technology, adapted here for InGaAs Schottky contacts, has improved the ideality factor (η) and yield relative to conventional evaporated Pt. With 810 μW of local oscillator power, applied to the diode, and zero DC bias, an integrated InGaAs mixer/antenna demonstrated an excellent diode performance of 199 K RF input double-sideband noise temperature with a corresponding single-sideband (SSB) conversion loss (L_c) of 5.0 dB at LO, RF, and IF frequencies of 94 GHz, 94 GHz±1.4 GHz, and 1.4 GHz, respectively. Likewise, the diodes in an InGaAs subharmonic integrated mixer/antenna demonstrated an equivalent RF-port double-sideband (DSB) noise temperature (T_mix) of 1058 K and single-sideband conversion loss of 10.2 dB at 180 GHz with a 90-GHz LO power (PLO) of 1.6 mW. Compared to GaAs diodes with RF coupling and IF losses removed, the single-ended InGaAs noise temperature results were within 46-100 K of those for state-of-the-art GaAs mixer diodes while requiring significantly less LO power     

Uncooled InAs-GaSb type-II infrared detectors grown on GaAssubstrates for the 8-12-μm atmospheric window

We report on the growth and characterization of type-II infrared detectors with an InAs-GaSb superlattice active layer for the 8-12-μm atmospheric window at 300 K. The material was grown by molecular beam epitaxy on semi-insulating GaAs substrates. Photoconductive detectors fabricated from the superlattices showed 80% cutoff at about 12 μm at room temperature. The responsivity of the device is about 2 mA/W with a 1-V bias (E=5 V/cm) and the maximum measured detectivity of the device is 1.3×10⁸ cm.Hz^1/2/W at 11 μm at room temperature. The detector shows very weak temperature sensitivity. Also, the extracted effective carrier lifetime, τ=26 ns, is an order of magnitude longer than the carrier lifetime in HgCdTe with similar bandgap and carrier concentration     

A self-aligned gate GaAs MESFET with p-pocket layers forhigh-efficiency linear power amplifiers

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz π/4-shift QPSK modulated input     

Submicrometer GaAs MESFET with shallow channel and very high transconductance

A 0.5-µm GaAs MESFET with a 25-nm thin channel, 400- mS/mm maximum transconductance, and 580-mS/V.mm K value is presented. This extremely high K value was obtained using an electron-beam fabricated recessed-gate MESFET structure on a highly doped (9.10¹⁷cm^-3) MBE-grown channel layer with 2600-cm²/V.s mobility. The use of thin channels and a buried p-layer also reduced the output conductance and other short-channel effects dramatically. As a result, these scaled MESFET's are very promising for high-speed digital logic circuits.     

Microwave performance of ion-implanted InP JFETs

These devices have a planar structure with the channel and gate regions formed by the selective implantation of silicon and beryllium into an Fe-doped semi-insulating InP substrate. The nominal gate length is 2 μm with a channel doping of 10¹⁷ cm^-3 and thickness of 0.2 μm. The measured values of f_T and f_max are 10 and 23 GHz, respectively. Examination of the equivalent circuit parameters and their variation with bias led to the following conclusions: (a) a relatively gradual channel profile results in lower than desired transconductance, but also lower gate-to-channel capacitance; (b) although for the present devices, the gate length and transconductance are the primary performance-limiting parameters, the gate contact resistance also reduces the power gain significantly; (c) the output resistance appears lower than that of an equivalent GaAs MESFET, and requires a larger V_DS to reach its maximum value; and (d) a dipole layer forms and decouples the gate from the drain with a strength that falls between that of previously reported GaAs MESFETs and InP MESFETs