An Optical Interconnect Transceiver at 1550 nm Using Low-Voltage Electroabsorption Modulators Directly Integrated to CMOS

A low-voltage, 90-nm CMOS optical interconnect transceiver operating at 1550-nm optical wavelength is presented. This is the first demonstration of a novel optoelectronic modulator architecture (the quasi-waveguide angled-facet electroabsorption modulator) in a system. It features a simple electronic packaging via flip-chip bonding to silicon. Devices have a broad optical bandwidth, are arrayed two dimensionally, and feature surface normal, spatially separated, and misalignment-tolerant optical ports. The modulators are driven with a novel pulsed-cascode driver capable of supplying an output-voltage swing of 2 V (twice the nominal 1-V CMOS supply) without overstressing thin-oxide core CMOS devices. At the receiver side, a sensitivity of -15.2 dBm is obtained with an integrating/double-sampling front end. The transceiver includes clock generation and recovery circuitry that enables a data serialization factor of five. At a maximum data rate of 1.8 Gb/s, the optical transmitter, receiver, and clocking circuitry consume 12.6, 4.5, and 6.5 mW, respectively, for a total link electrical power dissipation of 23.6 mW. To the best of our knowledge, this is the first demonstration of an interconnect transceiver operating at 1550 nm with a III-V output device directly integrated to the CMOS.     

Polymer micro-ring filters and modulators

Micro-ring wavelength filters and resonant modulators using polymer materials at 1300 nm and 1550 nm are analyzed, designed, and demonstrated. The rings are integrated with vertically coupled input and output waveguides. The devices are fabricated using optical lithography. Filters with a finesse of 141 and free spectral range of 5 nm at 1300 nm and finesse of 117 with a free spectral range (FSR) of 8 nm at 1550 nm are demonstrated. Ring resonators with a Q as high as 1.3 /spl times/ 10/sup 5/ at 1300 nm are demonstrated. The filters can be temperature tuned at the rate of 14 GHz//spl deg/C. Resonant ring modulators, which use an electrooptic polymer, are demonstrated. The resonance wavelength voltage tunes at the rate of 0.82 GHz/V. The modulators have a bandwidth larger than 2 GHz. Using the resonant modulator, and open eye diagram at 1 Gb/s is demonstrated.     

Large-scale WDM star-based photonic ATM switches

This paper describes the large-scale photonic asynchronous transfer mode (ATM) switching systems being developed in NTT Laboratories. It uses wavelength division multiplexing (WDM) techniques to attack 1 TB/s throughput. The architecture is a simple star with modular structure and effectively combines optical WDM techniques and electrical control circuits. Recent achievements in important key technologies leading to the realization of large-scale photonic ATM switches based on the architecture are described. We show that we can obtain a 320 Gb/s system that can tolerate the polarization and wavelength dependencies of optical devices. Our experiments using rack-mounted prototypes demonstrate the feasibility of our architecture. The experiments showed stable system operation and high-speed WDM switching capability up to the total optical bandwidth of 12.8 nm, as well as successful 10 Gb/s 4×4 broadcast-and-select and 2.5 Gb/s 16×16 wavelength-routing switch operations     

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm².     

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.     

Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications

On the basis of a realized 12$,times,$ 10 Gb/s card-to-card optical link demonstrator, the capabilities of a polymer-waveguide-based board-level optical interconnect technology are presented. The conception and realization of the modular building blocks required for this board-level optical interconnect technology are described in detail. In particular, we report on the fabrication and characterization of board-integrated optical low-loss polymer waveguides that are compatible with printed circuit board (PCB) manufacturing processes. We also explain our fully passive alignment technique, superseding time-consuming active positioning of components and connectors. To realize optical transceiver modules comprising vertical cavity surface emitting laser (VCSEL) arrays with laser drivers and photodetector arrays with transimpedance amplifiers (TIAs), a mass-production concept based on wafer-level processing has been elaborated and successfully implemented.      

High-Speed Optical Interconnect Coupler Based on Soft Lithography Ribbons

In this paper, high-speed optical ribbon couplers for card-to-backplane interconnect applications are presented. The ribbon couplers are based on evanescent coupling between flexible multimode waveguide arrays. A soft lithographic technique is utilized to fabricate the ribbons. A flexible nonterminating optical data bus has been developed. Using BeamPROP software, we simulated the evanescent light coupling between two closely spaced ribbon waveguides to study the effects of waveguides separation, interaction length, and misalignment on coupling efficiency. Further experimental analysis and tests have been performed to quantify these effects. To investigate data transmission performance, a 12-channel optical interconnect link has been assembled. Experimental results demonstrated successful evanescent coupling; facilitating auto alignment coupling between card and backplane ribbon waveguides at data speeds as high as 10 Gb/s per channel. The evident high-speed interconnect performance and rapid ribbon prototyping approach can result in overall lower cost coupler fabrication for prospective optical interconnect applications.      

On-Chip Optical Interconnect

We describe a cost-effective and low-power-consumption approach for on-chip optical interconnection. This approach includes an investigation into architectures, devices, and materials. We have proposed and fabricated a bonded structure of an Si-based optical layer on a large-scale integration (LSI) chip. The fabricated optical layer contains Si nanophotodiodes for optical detectors, which are coupled with SiON waveguides using surface-plasmon antennas. Optical signals were introduced to the optical layer and distributed to the Si nanophotodiodes. The output signals from the photodiodes were sent electrically to the transimpedance-amplifier circuitries in the LSI. The signals from the photodiodes triggered of the circuitries at 5 GHz. Since electrooptical modulators consume the most power in on-chip optical interconnect systems and require a large footprint, they are critical to establish on-chip optical interconnection. Two approaches are investigated: 1) an architecture using a fewer number of modulators and 2) high electrooptical coefficient materials.     

Power minimization and technology comparisons for digitalfree-space optoelectronic interconnections

This paper investigates the design optimization of digital free-space optoelectronic interconnections with a specific goal of minimizing the power dissipation of the overall link, and maximizing the interconnect density. To this end, we discuss a method of minimizing the total power dissipation of an interconnect link at a given bit rate. We examine the impact on the link performance of two competing transmitter technologies, vertical cavity surface emitting lasers (VCSELs) and multiple quantum-well (MQW) modulators and their associated driver-receiver circuits including complementary metal-oxide-semiconductor (CMOS) and bipolar transmitter driver circuits, and p-n junction photodetectors with multistage transimpedance receiver circuits. We use the operating bit-rate and on-chip power dissipation as the main performance measures. Presently, at high bit rates (>800 Mb/s), optimized links based on VCSELs and MQW modulators are comparable in terms of power dissipation. At low bit rates, the VCSEL threshold power dominates. In systems with high bit rates and/or high fan-out, a high slope efficiency is more important for a VCSEL than a low threshold current. The transmitter driver circuit is an important component in a link design, and it dissipates about the same amount of power as that of the transmitter itself. Scaling the CMOS technology from 0.5 μm down to 0.1 μm brings a 50% improvement in the maximum operating bit rate, which is around 4 Gb/s with 0.1 μm CMOS driver and receiver circuits. Transmitter driver circuits implemented with bipolar technology support a much higher operating bandwidth than CMOS technology; they dissipate, however, about twice the electrical power. An aggregate bandwidth in excess of 1 Tb/s-cm² can be achieved in an optimized free-space optical interconnect system using either VCSELs or MQW modulators as its transmitters     

An Experimental Validation of a Wavelength-Striped, Packet Switched, Optical Interconnection Network

We experimentally validate a complete optical packet switched interconnection network, implementing the SPINet architecture. The scalable photonic integrated network (SPINet) architecture capitalizes on wavelength division multiplexing (WDM) to provide very large transmission bandwidths, simplify network design, and reduce the network's power dissipation. Contention resolution is performed in the optical domain, and a novel physical layer acknowledgement protocol is employed to mitigate the associated latency and performance penalties. Moreover, the SPINet architecture is specifically designed to enable on-chip integration by not using any kind of optical delay lines. Experiments presented include a complete functionality verification, error-free routing of 80 Gb/s wavelength-striped optical packets (8 wavelengths each modulated at 10 Gb/s) with a bit-error rate (BER) better than 10^-12, and novel performance-enhancement techniques such as path adjustments and load balancing.     

Digital optical networks using photonic integrated circuits (PICs) address the challenges of reconfigurable optical networks

To reduce costs and simplify operations, carriers are deploying flexible optical networks that can be easily reconfigured and managed remotely. This article provides an overview of typical all-optical reconfigurable optical add/drop multiplexer (ROADM) systems and their associated network issues. We describe a novel digital optical network architecture based on digital ROADM systems, which use photonic integrated circuits (PICs) to overcome many of these issues. Digital ROADM systems use monolithic PICs to integrate over 60 discrete optical components, including lasers, modulators and detectors, into a single pair of optical components, allowing cost-effective optical-electrical-optical conversion at every node. This also allows key functions such as service reconfiguration, add/drop and protection to be implemented in the digital domain, and enables de-coupling of service provisioning from optical link engineering, termed bandwidth virtualization. Finally, key deployment, reliability and operational metrics for PIC-based digital ROADM systems are presented.     

A novel scheme of all optical header extraction for optical packet switching network

A novel scheme of all optical header extraction using a semiconductor optical amplifier-Mach-Zehnder-Interferometer with asymmetric control light is proposed for optical packet switching with all-optical header processing at a header rate of 20 Gb/s and payload rate of 80 Gb/s in this article. The scheme parameters are discussed and analyzed to optimize the performance of optical header extraction with the proposed scheme. Numerical analysis and simulation show that a more than 17 dB contrast ratio can be achieved for the optical header separation when the input optical signal energy is as low as 0.2 pJ. In addition, the system structure is simple, stable, and photonic integratable.     

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.     

Electrooptic modulation of multisilicon-on-insulator photonic wires

This paper proposes and analyzes electrically modulated submicrometer-size high-index-contrast waveguides (photonic wires) based on a multisilicon-on-insulator (MSOI) platform. Metal-oxide-semiconductor junctions are used to control the effective refractive index of the waveguides. The electrooptic structures are electrically and optically modeled. The performances of the studied configurations are analyzed and compared in terms of phase modulation efficiency, optical losses, and operation speed, and the feasibility of their fabrication is discussed. Calculations indicate that the proposed schemes can be used to achieve highly efficient phase shifters (V/sub /spl pi//L/sub /spl pi//<1 V-cm) based on photonic wires on MSOI, with data transmission rates ranging from 3 to 10 Gb/s.     

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- $mu$m complementary metal–oxide–semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5–10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5–48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80–1.52 pJ/b. This work demonstrates a 15.0%–67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.      

Breakthrough technologies for the high-performance electrical ATMswitching system

A high-performance electrical asynchronous transfer mode (ATM) switching system is described with the goal of Tb/s ATM switching. The first step system was to use advanced Si-bipolar very large scale integrated (VLSI) technologies and the multichip technique. 1.0 μm bipolar SST technologies and Cu-polyimide multilayer MCM realized a 160 Gb/s throughput ATM system. The performance limitations of the 160 Gb/s system were power supply/cooling and module interconnection. The new ATM switching system, named OPTIMA-1, adopted optical interconnection/distribution to overcome the limitations and achieve 640 Gb/s. The system uses high-performance complementary metal-oxide-semiconductor (CMOS) devices and optical wavelength division multiplexing (WDM) interconnection. Combining OPTIMA-1 with optical cell-by-cell routing functions, i.e., photonic packet routing, can realize variable bandwidth links for 5 Tb/s ATM systems. This paper first reviews high-performance electrical ATM (packet) switching system architecture and hardware technologies. In addition, system limitations are described. Next, the important breakthrough technology of optical WDM interconnection is highlighted. These technologies are adopted to form OPTIMA-1, a prototype of which is demonstrated. The key technologies of the system are advanced 80 Gb/s CMOS/MCM, electrical technologies, and 10 Gb/s, 8 WDM, 8×8 optical interconnection. Details of implementation technologies are also described. Optical cell-by-cell (packet-by-packet) routing is now being studied. From the architectural viewpoint, dynamic link bandwidth sharing will be adopted. In addition, an AWG that performs cell-by-cell routing and a distributed large scale ATM system are realized. Optical routing achieves the 5 Tb/s needed in future B-ISDN ATM backbone systems     

Thermal Aging Reliability of Package-Level Polymer Optical Waveguides

Polymer optical waveguides are viewed as a potential interconnect solution in board-level optoelectronic systems. In this paper, the optical loss changes in siloxane polymer waveguides during thermal aging conditions are studied for the wavelengths of 850 and 1310 nm. The optical loss in waveguides during intended operation and temperature exposure can increase due to factors such as oxidation of waveguides, increased absorption, and scattering. In addition to these inherent changes in the optical properties of the waveguides, physical failures such as delamination and cracking of waveguides will also increase the optical loss. This paper focuses on the first set of parameters that affects the optical loss and as a first step; the optical absorption of the polymer material is characterized through spectroscopy experiments. The thermal-aging dependent optical loss is determined for waveguide samples at several different accelerated temperature conditions. The temperature contours in a polymer waveguide with an embedded laser are determined from experiments as well as finite-element modeling. Using experimental data, analytical models have been developed that relate the optical loss with temperature and time, and provide a practical way of determining the reliability of the optical waveguides during field-use conditions.     

硅基集成光电子器件的新进展

综述了硅基微纳激光器、调制器、探测器及光传输控制器件的最新研究进展.重点阐述了表面等离子体、量子阱、光子晶体及纳米光栅等新型结构在提高器件综合性能和降低器件尺寸方面的重大作用.同时,还展示了用标准互补金属氧化物半导体(CMOS)技术,实现硅基光子器件和电子器件在同一基片上微纳集成的巨大前景.     

All-optical pulse width and wavelength conversion at 10 Gb/s usinga nonlinear optical loop mirror

An all-optical pulse width and wavelength converter is demonstrated using a nonlinear optical loop mirror. The conversion of a 10 Gb/s, 8 ps pulse width data stream at 1551 nm to a 23 ps pulse width data stream at 1543 nm is demonstrated. The control pulse energy required for switching is 10 pJ. Bit-error-rate measurements are presented