Performance analysis of a duplex multicast switch

A multicast switching architecture called a duplex multicast switch is proposed, and several switch control algorithms are developed. A duplex multicast switch, with two point-to-point routing nets, has potential to provide significantly better performance than a simplex multicast switch by reducing the output loadings of routing nets. To fully realize its potential, two call distribution algorithms, cluster distribution and spread distribution, are developed. Cluster distribution is partitioned into partial search cluster distribution and exhaustive search cluster distribution based on search policies, and the performance of the three algorithms is analyzed by the arrival modulation technique. The results show that a spread distribution eliminates most slot contention blocking and achieves near-optimal performance     

Performance of a large multicast ATM switch

In this paper, we present the design of a large self-routing multicast ATM switch. The switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network built using small sized shared memory that can be used as a building block for a large sorting network. Small sized shared memory is also used in the 3-stage routing network making the switch modular and easy to implement using current VLSI technology. As the network uses shared memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely shared memory switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss ratio than the completely shared memory switch under moderate to heavy traffic load (0.6 ≤ effective offered load ≤ 1.2). Furthermore, multicast cell delays are drastically improved. This revised version was published online in June 2006 with corrections to the Cover Date.     

Design and analysis of a growable multicast ATM switch

This work designs and analyzes a cost-effective growable multicast asynchronous transfer mode (ATM) switch that has a new grouping network structure. The proposed switch can easily be enlarged by using more stages, since both cell routing and contention resolution are designed to distribute over the switch elements. Experimental results indicate that, by allowing valid cells to enter grouping networks from two directions (the west and north sides), the modular ATM switch proposed herein not only meets the ATM performance requirements for both unicasting and multicasting but also uses fewer switch elements and has a shorter cell delay than the ATM switch     

Performance analysis of k-fold multicast networks

Multicast involves transmitting information from a single source to multiple destinations, and is an important operation in high-performance networks. A k-fold multicast network was recently proposed as a cost-effective solution to providing better quality-of-service functions in supporting real-world multicast applications. To give a quantitative basis for network designers to determine the suitable value of system parameter k under different traffic loads, in this paper, we propose an analytical model for the performance of k-fold multicast networks under Poisson traffic. We first give the stationary distribution of network states, and then derive the throughput and blocking probability of the network. We also conduct extensive simulations to validate the analytical model, and the results show that the analytical model is very accurate under the assumptions made. The analytical and simulation results reveal that by increasing the fold of the network, network throughput increases very fast when the fanouts of multicast connections are relatively small, compared with the network size.     

Odd-even input-buffered multicast switch

An input buffered packet switch called the odd-even multicast switch is proposed. The packet splitting probability of the proposed switch is derived and the packet output contention is resolved using the cyclic-priority reservation (CPR) algorithm. The throughput and mean packet delay of the proposed switch are compared with a simple input buffered switch. It is found that the proposed switch gives a significant performance improvement at the expense of extra packet splitting overhead     

Call scheduling algorithms in a multicast switch

Multicast switching is emerging as a new switching technology that can provide efficient transport in a broadband network for video and other multipoint communication services. The authors develop and analyze call scheduling algorithms for a multicast switch. In particular, they examine two general classes of scheduling algorithms: call packing algorithms and call splitting algorithms. The performance improvement by the call packing algorithms examined is shown to be negligible. In contrast, the call splitting algorithms can provide significantly lower blocking by reducing the level of output port contention. However, excessive call splitting could degrade performance because of the additional load introduced to the input ports. The authors present a simple call splitting algorithm called greedy splitting which achieves near-optimal performance     

Design of multicast ATM switch

The architecture of a shared multibuffer ATM switch that uses the cyclic address queue method is described. No memory speedup is required. The blocking effect is eliminated for unicast traffic. Multicast functions are efficiently carried out via a multicast queue. A dynamic scheme is used to improve the unfairness problem     

Design of multicast ATM switch

The proposed ATM switch has very high throughput under heavy-traffic conditions. The cell blocking scenario described in the comment [see ibid., vol. 35, no 5, 1999] is of no importance. Directly after the switch is reset, the first four cells will not be placed in the same RAM with the help of the cell-in stage. Under heavy-traffic conditions, the number of cells in each RAM is well balanced and no blocking effect would occur for unicast traffic. That scenario would only arise at the end of transmission when no more cells would be entering the switch. However, the probability of that scenario ocurring is extremely low. Therefore, an internal memory speedup would not be needed and the throughput would not be degraded. The proposed dynamic multicast scheme can fully utilise the available bandwidth     

A multicast broadband packet switch

A multicast broadband packet switch architecture is proposed. It has the following attractive features: little extra cost compared to a unicast switch, fast packet duplication, and easy addition and deletion of calling parties. A simulation study of this multicast system is presented to verify its performance     

Performance analysis of optical multicast in a new switching structure

The emergence of new services demands multicast function in optical network.Because of the high cost and complex architecture of multicast capable (MC) node, splitter-sharing switch structure is introduced in which the light splitters are shared by all input signals.To accommodate to this situation, by extending resource ReSerVation protocol-traffic engineering (RSVP-TE) and open shortest path first-traffic engineering (OSPF-TE), a new optical multicast mechanism is provided and the signaling flow and its finite state machine model are given.At the same time, a multicast routing algorithm in splitter-sharing optical network and a changing link weight policy to balance network traffic are proposed.Simulations in NSFNET show no matter with or without wavelength converters, when the number of splitters is 25% of that demanded by traditional MC nodes, the multicast performance has been close to the ideal circumstance.Wavelength converters and changing link weight help much in improving the traffic performance when the number of splitters is adequate.     

Clos-based fault tolerant multicast ATM switch

A Clos-based fault tolerant multicast ATM switch is proposed in which each stage has one more redundant switch module. If one switch module is faulty, the redundant module replaces the faulty module. On the other hand, even under fault-free conditions, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance     

A large scalable ATM multicast switch

This paper focuses on designing a large N×N high-performance broad-band ATM switch. Despite advances in architectural designs, practical switch dimensions continue to be severely limited by both the technological and physical constraints of packaging. Here, we focus on augmentation in a “single-switch” design: we provide ways to construct arbitrarily large switches out of modest-size components and retain overall delay/throughput performance. We propose a growable switch architecture based on several key principles: 1) the knockout principle exploits the statistical behavior of cell arrivals, and thereby reduces the interconnect complexity; 2) output queueing yields the best possible delay/throughput performance; 3) distributed control in routing (multicast) cells through the interconnect fabric without internal path conflicts; and 4) simple basic building blocks facilitate scalability. Other attractive features of the proposed architecture include: 1) intrinsic broadcast and multicast capabilities; 2) built-in priority sorting functionality; and 3) the guarantee of first-in, first-out cell sequence, To achieve 10^-14 cell loss probability, only maximum size 32×16 basic building modules are required, and no crossover interconnects exist between modules in a three-dimensional configuration     

The design and analysis of an ATM multicast switch with adaptivetraffic controller

The paper describes several improvements to a nonblocking copy network proposed previously for multicast packet switching. The improvements provide a complete solution to some system problems inherent in multicasting. The input fairness problem caused by overflow is solved by a cyclic running adder network (CRAN), which can calculate running sums of copy requests starting from any input port. The starting point can change adaptively in every time slot based on the overflow condition of the previous time slot. The CRAN also serves as a multicast traffic controller to regulate the overall copy requests. The throughput of a multicast switch can be improved substantially if partial service of copy request is implemented when overflow occurs. Call-splitting can also be implemented by the CRAN in a straightforward manner. Nonuniform distribution of replicated packets at outputs of the copy network may affect the performance of the following routing network. This output fairness problem due to underflow is solved by cyclically shifting the copy packets in every time slot. An approximate queueing model is developed to analyze the performance of this improved copy network. It shows that if the loading on each output of the copy network is maintained below 80%, the average packet delay in an input buffer would be less than two time slots     

A photonic front-end processor in a WDM ATM multicast switch

Dense wavelength-division multiplexing (DWDM) technology has provided tremendous transmission capacity in optical fiber communications. However, switching and routing capacity is still far behind transmission capacity. This is because most of today's packet switches and routers are implemented using electronic technologies. Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity. In this paper, we present a photonic asynchronous transfer mode (ATM) front-end processor that has been implemented and is to be used in an optically transparent WDM ATM multicast (3M) switch. We have successfully demonstrate the front-end processor in two different experiments. One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s. The other performs cell synchronization, where cells from different input ports running at 2.5 Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric. The resolution of alignment is achieved to the extent of 100 ps (or 1/4 bit). An integrated 1×2 Y-junction semiconductor optical amplifier (SOA) switch has been developed to facilitate the cell synchronizer     

On the speedup required for a multicast parallel packet switch

A parallel packet switch (PPS) is a switch in which the memories run slower than the line rate. Arriving packets are load-balanced packet-by-packet over multiple lower speed center stage packet switches. It is known that, for unicast traffic, a PPS can precisely emulate a FCFS output-queued (OQ) switch with a speedup of two and an OQ switch with delay guarantees with a speedup of three. In this paper we ask: is it possible for a PPS to emulate the behavior of an OQ multicast switch? The main result is that for multicast traffic an N-port PPS can precisely emulate a FIFO OQ switch with a speedup of S>2√N+1, and a switch that provides delay guarantees with a speedup of S>2√(2N)+2     

A practical version of Lee's multicast switch architecture

Several improvements to T.T. Lee's (1988) multicast switch architecture are described. The improvements make Lee's architecture practical, allowing it to achieve maximum network throughput under worst-case conditions and vastly reducing the amount of memory required for the addressing of multicast cells. These improvements allow multicast to be added to a 256-port switch with 150-Mb/s links at a cost of about two additional chips per port     

Design of multicast ATM switch [comment]

The authors of the original paper [see ibid., vol. 34, no. 22, p. 2090-1, 1998] proposed a shared multi-buffer asynchronous transfer mode (ATM) switch that uses the cyclic address queue method. In this comment we show that the proposed architecture has several shortcomings: loss of cell sequence, blocking effect at the read-out stage, and high hardware cost/complexity     

Performance of a broadcast packet switch

The results of a simulation study undertaken to evaluate a high-performance packet-switching fabric supporting point-to-point and multipoint communications are presented. This switching fabric contains several components, each based on conventional binary routing networks. The most novel element is the copy network, which performs the packet replication needed for multipoint connections. Results characterizing the performance of the copy network are presented. Several architectural alternatives for conventional binary routing networks are also evaluated. For example, the performance gains obtainable by using cut-through switching in the context of binary routing networks with small buffers are quantified. One surprising result is that networks constructed from nodes with more then two input and output ports can perform less well than those constructed from binary nodes. This result is quantified and explained     

The fast packet ring switch: a high-performance efficientarchitecture with multicast capability

An architecture is presented for the packet switching of integrated traffic. It is based on the asynchronous routing of packets of varying size through regularly recurring dedicated time slots provided by a simple slotted-ring system. The architecture implements the distributed buffering and processing of packets, is data driven, and is designed to exploit fully the limited bandwidth of the ring system. Thus, switch modules of reasonable size and throughput are made feasible. The switch modules can be easily interconnected to achieve sufficient throughput for networking of services such as voice, data, image, and videoconferencing. The architecture provides a simple modular switching structure which does not suffer from the topological complexities and bottlenecks of those that use the staged Banyan-type networks for the switching of packets. Quasicircuit-switching can easily be achieved through selected ports with a peak bit-rate bandwidth allocation strategy in the switch control. Multicasting in particular is made simple and efficient in the current architecture. Moreover, it provides for the selective queueing of packets in the transmit ports