点对多点服务的输入/输出排队ATM交换机性能分析

本文分析了一种具有点对多点服务能力的内部无阻塞输入／输出排队ATM交换机在反压控制下的性能指标。在每个输入端口信元的到达具有相同的强度，每个排头信元以一种相同的概率分布函数被复制成多个输往不同的输出端口的排头信元，复制后的排头柜元到达输出端口的概串相同为1/N，且输入、物出缓冲容量均为有限。为保证交换机内部不发生信元丢失，引入了反压机制（Backpressure）。本文利用矩阵几何分析法绘出了数值解，计算机仿真结果表明理论分析是正确的。     

Analysis of nonblocking ATM switches with multiple input queues

An analytical model for the performance analysis of a multiple input queued asynchronous transfer mode (ATM) switch is presented. The interconnection network of the ATM switch is internally nonblocking and each input port maintains a separate queue of cells for each output port. The switch uses parallel iterative matching (PIM) to find the maximal matching between the input and output ports of the switch. A closed-form solution for the maximum throughput of the switch under saturated conditions is derived. It is found that the maximum throughput of the switch exceeds 99% with just four iterations of the PIM algorithm. Using the tagged input queue approach, an analytical model for evaluating the switch performance under an independent identically distributed Bernoulli traffic with the cell destinations uniformly distributed over all output ports is developed. The switch throughput, mean cell delay, and cell loss probability are computed from the analytical model. The accuracy of the analytical model is verified using simulation     

输入/输出ATM交换机在突发性业务下的性能

本文详尽分析了内部无阻塞输入／输出排队反压型ＡＴＭ交换机在突发性业务下信元丢失、交换机最大吞吐量等性能。输入端口信元的到达过程是ＯＮ－ＯＦＦ突发流，且ＯＮ态以概率ｐ发送信元，ＯＮ－ＯＦＦ长度为Ｐａｒｅｔｏ分布的随机变量；属于同一突发流的信元输往同一个输出端口，不同突发流的信元等概率输往不同的输出端口；输入／输出缓冲器长度有限，交换机加速因子Ｓ任意。本文同时比较了突发长度为周期／几何分布下的交换机性能，其结论对实际设计一输入／输出排队反压型ＡＴＭ交换机具有一定参考意义。     

High Power, Magnetic Field Controlled Microwave Gas Discharge Switches

A new type of gas discharge switch is described, It is electronically controllable, broadband, and capable of rapidly switching high power pulsed microwaves from either of two waveguide input ports to a single waveguide output port, or from one waveguide input port to either of two waveguide output ports. The electronic control is achieved by turning on or off a magnetic field set for cyclotron resonance. An approximate analysis is given of the operation of the active element of the switch and the results are compared with experiment. An analysis of the effects of frequency scaling indicates that, with the exception of the magnetic flux density which increases with increasing frequency, the switch parameters either improve or remain unchanged in going to higher frequencies. Two different switch configurations are investigated, one a Y-junction switch for operation at S band and the other a balanced top-wall hybrid coupler switch for operation at K/sub u/ band. Their electrical characteristics are described.     

A combined input and output queued packet switched system based on PRIZMA switch on a chip technology

A packet-switched system architecture based on the combination of a single-chip output-buffered switch element and input queues that sort arriving packets on a per-output-port basis is proposed. Scheduling is performed in a distributed two-stage approach. Independent arbiters at each of the inputs resolve input contention. Whereas the output-buffered switch element resolves output contention. As a result of this distribution of functionality, complexity of the input arbiters is only linearly proportional to the number of output ports N, thus offering better scalability than purely input-buffered approaches that require complex centralized schedulers. Since the input queues are used as the main buffering mechanism, only a relatively small amount of memory (on the order of N/sup 2/ packet locations) is required in the shared-memory switch, allowing high-throughput implementations. We present simulation results to demonstrate the high performance and robustness under bursty traffic achieved with the proposed system architecture. A practical implementation in the form of the PRIZMA family of switch chips is outlined, with emphasis on its versatility in scaling in terms of both port speed and number of ports, and its support for quality-of-service mechanisms.     

Simultaneous fast wavelength switching and intensity modulationusing a tunable DBR laser

The use of a three-section distributed Bragg reflector (DBR) laser to switch wavelengths rapidly and simultaneously transmit data by intensity modulation is discussed. This combination simulates the operation of a tunable transmitter in a multiwavelength packet switch. In this type of switch, each output port is tuned to receive data on a unique, fixed wavelength; packets are routed from input ports to the appropriate output ports by wavelength addressing. In each transmission cycle, the input port transmitter tunes to the wavelength associated with the intended output port and subsequently broadcasts the data packet. Limitations on various system parameters, such as the number of allowed channels, the wavelength switching times, and packet lengths (residency times), as determined by thermally-induced wavelength drifts are also discussed. The advantages of using a single device for both fast wavelength switching and direct data modulation are significant: the elimination of external modulators improves both the simplicity of the implementation and the available power budget     

Computing approximate blocking probabilities for transparent waveband switching based WDM networks using hierarchical cross-connects

An analytical model is presented to study the dynamics of wavelength division multiplexing (WDM) networks with waveband switching (WBS). The reduced load approximation method is considered to compute approximated network blocking probabilities in WBS-based WDM networks. The analytical model considers the link blocking probability due to insufficient link capacity and an impact of the waveband granularity (G). The analytical model also considers the node blocking probability due to unavailability of a switch port at the wavelength cross connect (WXC) layer of an Hierarchical cross connect (HXC) switch node. The set of nonlinear equations is obtained with the link independence assumption and solved using repeated substitutions. The accuracy of the analytical model is examined by comparing with simulation results considering the random-fit algorithm for waveband and wavelength assignments in different network scenarios. Lightpaths are routed between source and destination (s-d) HXC switch nodes using shortest path first (SPF) routing. An impact of the switch parameter to limit the input and the output WXC switch ports of an HXC switching node is also being investigated using the analytical model as well as through simulation results.     

Analysis of packet switches with input and output queuing

A single-stage nonblocking N*N packet switch with both output and input queuing is considered. The limited queuing at the output ports resolves output port contention partially. Overflow at the output queues is prevented by a backpressure mechanism and additional queuing at the input ports. The impact of the backpressure effect on the switch performance for arbitrary output buffer sizes and for N to infinity is studied. Two different switch models are considered: an asynchronous model with Poisson arrivals and a synchronous model with Bernoulli arrivals. The investigation is based on the average delay and the maximum throughput of the switch. Closed-form expressions for these performance measures are derived for operation with fixed size packets. The results demonstrate that a modest amount of output queuing, in conjunction with appropriate switch speedup, provides significant delay and throughput improvements over pure input queuing. The maximum throughput is the same for the synchronous and the asynchronous switch model, although the delay is different.<>     

Protection-against-collision optical packet network

An optically transparent packet network controlled by a simple medium access circuit is presented. The system, based on frequency division multiplexing and tunable transmitters, has no internal blocking and is optically self-routing. It provides internal collision-free traffic by allowing access to the network only if the addressed channel (output port) is available. A packet denied access to the network is reflected back to its input port, which is thus informed of the packet status. Therefore, the traffic is not bogged down by acknowledgments between input and output ports. To achieve this result, each input of the network is controlled by a protection-against-collision (PAC) circuit located at a central hub. The PAC circuit uses the packet for probing the energy present in the addressed channel. The resulting signal controls an optical switch connecting the input port to the network. Thus, full optical connectivity is provided between ports controlled by electrical signals derived from simple optical power measurements     

Design and implementation of Abacus switch: a scalable multicastATM switch

Describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32×32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz     

Derivation of the mean cell delay and cell loss probability formultiple input-queued switches

The multiple input-queued (MIQ) asynchronous transfer mode (ATM) switch has drawn much interest as a promising candidate for a high-speed and high-performance packet switch. The most conspicuous feature of the switch is that each input port is equipped with m(1⩽m⩽N) distinct queues, each for a group of output ports. Since the MIQ switch has multiple queues, an input can serve up to m cells in a time slot, leading to an enhanced performance. We derive the average queue length, mean cell delay, and cell loss probability for the MIQ switch in terms of the number of queues in an input port (m) and input load. The results include a special case of the single input-queued (SIQ) switch (m=1), which is analyzed by Hui et al. (1987)     

8端口ATM工作组交换机设计与性能分析

本文概述了基于FPGA的8端口155Mbit/s(25Mbit/s)ATM工作组交换机的设计,对其关键部分如输入输出端口处理,交换结构等进行了阐述,并对其性能进行了分析,试验运行表明各项指标均满足设计要求。     

Performance analysis of the multiple input-queued packet switch with the restricted rule

The multiple input-queued (MIQ) switch is the switch which manages multiple (m) queues in each input port, each of which is dedicated to a group of output ports. Since each input port can switch up to m cells in a time slot, one from each queue, it hardly suffers from the head-of-line (HOL) blocking which is known to be the decisive factor limiting the throughput of the single input-queued (SIQ) switch. As a result, the MIQ switch guarantees enhanced performance characteristics as the number of queues m in an input increases. However, the service of multiple cells from an input could cause internal speedup or expansion of the switch fabric, diluting the merit of high-speed operation in the conventional SIQ scheme. The restricted rule is contrived to circumvent this side effect by regulating the number of cells switched from an input port. We analyze the performance of the MIQ switch employing the restricted rule. For the switch using the restricted rule, the closed formulas for the throughput bound, the mean cell delay and average queue length, and the cell loss bound of the switch are derived as functions of m, by generalizing the analysis for the SIQ switch by J.Y. Hui and E. Arthurs (see IEEE J. Select. Areas Commun., vol.SAC-5, p.1262-73, 1987).     

RPA: a flexible scheduling algorithm for input buffered switches

This paper presents and evaluates a quasi-optimal scheduling algorithm for input buffered cell-based switches, named reservation with preemption and acknowledgment (RPA). RPA is based on reservation rounds where the switch input ports indicate their most urgent data transfer needs, possibly overwriting less urgent requests by other input ports, and an acknowledgment round to allow input ports to determine what data they can actually transfer toward the desired switch output port. RPA must be executed during every cell time to determine which cells can be transferred during the following cell time. RPA is shown to be as simple as the simplest proposals of input queuing scheduling, efficient in the sense that no admissible traffic pattern was found under which RPA shows throughput limitations, and flexible, allowing the support of packet-mode operations and different traffic classes with either strict priority discipline or bandwidth guarantee requirements. The effectiveness of RPA is assessed with detailed simulations in uniform as well as unbalanced traffic conditions and its performance is compared with output queuing switches and the optimal maximum weighted matching (MWM) algorithm for input-buffered switches. A bound on the performance difference between the heuristic weight matching adopted in RPA and MWM is analytically computed     

Dynamic buffer management using per‐queue thresholds

Shared buffer switches consist of a memory pool completely shared among output ports of a switch. Shared buffer switches achieve low packet loss performance as buffer space is allocated in a flexible manner. However, this type of buffered switches suffers from high packet losses when the input traffic is imbalanced and bursty. Heavily loaded output ports dominate the usage of shared memory and lightly loaded ports cannot have access to these buffers. To regulate the lengths of very active queues and avoid performance degradations, threshold‐based dynamic buffer management policy, decay function threshold, is proposed in this paper. Decay function threshold is a per‐queue threshold scheme that uses a tailored threshold for each output port queue. This scheme suggests that buffer space occupied by an output port decays as the queue size of this port increases and/or empty buffer space decreases. Results have shown that decay function threshold policy is as good as well‐known dynamic thresholds scheme, and more robust when multicast traffic is used. The main advantage of using this policy is that besides best‐effort traffic it provides support to quality of service (QoS) traffic by using an integrated buffer management and scheduling framework. Copyright © 2006 John Wiley & Sons, Ltd.     

Analysis of a Negative Conductance Amplifier Operated with a Nonideal Circulator

Negative conductance amplifiers are usually operated with a circulator in order to achieve greater gain-bandwidth products and stable operation. Typical circulators differ from ideal circulators in that the forward loss between ports is not zero, and the reverse isolation between ports is not intinite. The main effects of nonintinite isolation are shown to be a modified gain-bandwidth product and a assumed to exist between ports 3 and 2. No other dechange in output admittance of the circulator output port. These effects result principally from the finite isolation between the output and amplifier ports. The main effect of incidental dissipation has previously been shown to be an increase in system noise figure. This paper considers only the effects caused by noninfinite isolation. A model of a lossless three-port circulator with noninfinite isolation is set up, and a negative conductance amplifier is considered to be limited to ensure a positive output conductance at the output port of the circulator (that is, the combination of negative conductance amplifier and nonideal circulator is assumed to be open-circuit stable). Subject to this assumption, the combination of negative conductance amplifier and nonideal circulator is then analyzed for its output admittance, available power gain, and effective input noise temperature.     

Structural Fault Testing of Embedded Cores Using Pipelining

The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a bypass mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the accessibility (of the core input and output ports) is solved as a shortest path problem. Finally, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The experimental results show higher fault coverage and shorter test time.     

具有丢失优先级策略的输入／输出排队ATM交换机的性能分析

本文分析了一种输入排队缓冲器有丢失优先级的内部无阻塞输入／输出排队ＡＴＭ交换机在反压控制下的信元丢失指标。在每个输入端口高、低优先级信元的到达具有相同的强度，到达输出端口的概率相同为１Ｎ，且输入、输出缓冲容量均为有限。为保证交换机内部不发生信元丢失，引入了反压机制（Ｂａｃｋｐｒｅｓｓｕｒｅ）。文中表明，使用丢失优先级策略的交换机比纯输入／输出排队交换机更能满足不同业务服务等级ＱｏＳ（ＱｕａｌｉｔｙｏｆＳｅｒｖｉｃｅ）的丢失要求，而且所需缓冲容量减少。     

A high performance differential input CMOS current buffer

In this paper, a high accuracy CMOS differential input current buffer (CB) is proposed which employs super source followers (SSF) as input stage and regulated cascode (RGC) current mirrors as output stage. High accuracy requires very high output resistance and low input resistance. Small signal analysis is performed and it is shown that the proposed CB circuit has very low input impedances at ports n and p due to SSF transistors and also very high output impedance at output port due to RGC current mirrors. The simulation results show 9.72 Ω input resistances at ports n and p, 454 MΩ output resistance at output port with only 625 μW power consumption under ±0.9 V power supplies. The simulations are performed with HSpice using TSMC 0.18 μm process parameters and it is shown that the simulation results are in very good agreement with the theoretical ones.     

Speedup and buffer division in input/output queuing ATM switches

The capacity of a switch is built out of two factors: space parallelism and speedup. A switch has space parallelism if more than one input port can transmit simultaneously. Speedup is the ratio of the switch's internal link speed over the incoming link speed. An input-queuing switch uses only the first factor (space parallelism), and a share-medium or a share-memory output queuing switch uses only the second factor (speedup). However, to build a large switch, both factors are normally used. A large switch's capacity can be built with less space parallelism (the space factor), but more speedup (the time factor), or vise versa. Buffers are needed at both the input and the output ports. In this paper, we show how to divide the buffers between the input and the output queues and how the optimal division is affected by the (space, time) combinations.