国产A／D（模／数）,D／A／（数／模）转换器失效模式和失效 …

国产Ａ／Ｄ（模／数）Ｄ／Ａ（数／模）转换器是重点电子产品,属大规模集成电路。我国军用和重点工程对Ａ／Ｄ,Ｄ／Ａ的需求很大,而目前高位数和高精度的该类产品主要仍靠进口。本文通过研究其失效模式和失效机理,可暴露存在问题,总结经验教训,寻找改进措施,促进该类产品研制与生产水平的提高,以利于国产Ａ／Ｄ,Ｄ／Ａ的进一步开发和发展。     

国产A/D(模/数)、D/A/(数/模)转换器失效模式和失效机理研究

国产Ａ／Ｄ（模／数）、Ｄ／Ａ（数／模）转换器是重点电子产品,属大规模集成电路。我国军用和重点工程对Ａ／Ｄ、Ｄ／Ａ的需求很大,而目前高位数和高精度的该类产品主要仍靠进口。本文通过研究其失效模式和失效机理,可暴露存在问题,总结经验教训,寻找改进措施,促进该类产品研制与生产水平的提高,以利于国产Ａ／Ｄ、Ｄ／Ａ的进一步开发和发展。     

过采样∑－△A／D调制器

过采样∑－△Ａ／Ｄ调制器洪志良（复旦大学电子工程系，上海，２００４３３）１引言过采样∑－△Ａ／Ｄ变换器通过过采样以时间来交换精度，从而避免实现高精度Ａ／Ｄ变换器所需要的复杂性。∑－△调制器结构是迄今为止在数字ＶＬＳＩ技术中执行高精度Ａ／Ｄ变换最吸引人...     

V／F变换器与单片机实现的智能化高精度A／D转换器

文章主要介绍了Ｖ／Ｆ变换器与单片机相结合实现的高精度、高分辨率、低成本、隔离式Ａ／Ｄ转换器的接口技术。在阐述设计方法的同时，给出了实用电路和Ａ／Ｄ转换流程框图。     

带隙型集成电压基准源的应用

详细介绍了ＡＤ５８Ｘ系列带隙型电压基准源工作原理及有关参数定义，并以ＡＤ５８１和ＡＤ５８４为例，阐述基准源在Ａ／Ｄ转换、Ｄ／Ａ转换和高精度大电流源方面的应用。     

高精度PWM A/D转换

本文论述了单片机脉宽调制（ＰＷＭ）实现高精度低成本Ａ／Ｄ转换的原理，介绍了ＭＣ６８ＨＣ９０８ＧＰ３２的１４位ＰＷＭ　Ａ／Ｄ的硬件方法和软件结构。     

TLC32044在语音信号处理中的应用

文章介绍了高精度可编程Ａ／Ｄ、Ｄ／Ａ芯片ＴＬＣ３２０４４的性能特点、工作原理及其在语音处理中的应用     

JAVA的J／DIRECT的应用

介绍了ＪＡＶＡ利用Ｊ／Ｄｉｒｅｃｔ访问本地函数的方法构造一个声音播放类，可用于不同的场合。     

多步实现的A／D变换器

多步实现的Ａ／Ｄ变换器洪志良（复旦大学电子工程系，上海，２００４３３）１引言视频信号的数字处理、高速数字通信和家用电子网络的数据传输都需要高速数据，为获得和应用这些数据，需要实时处理的Ａ／Ｄ、Ａ／Ｄ变换器。全平行高速Ａ／Ｄ变换器由于需要２ｎ个高精度电...     

双频段CDMA/AMPS下变频器SA9500

双频段ＣＤＭＡ／ＡＭＰＳ下变频器集成电路ＳＡ９５００集成了用于双频段、三模式ＣＤＭＡ／ＡＭＰＳ蜂窝移动通信电话手机所必需的所有前端接收混频器,可工作高频段１９００ＭＨｚＰＳＣＣＤ－ＭＡ和低频段８００ＭＨｚＣＤＭＡ蜂窝移动通信系统,或模拟模中。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A stereo audio sigma-delta A/D-converter

A stereo sigma delta A/D-converter for audio applications is presented. In this converter, two identical cascaded fourth-order sigma-delta modulators and a sophisticated multistage linear-phase FIR decimation filter with oversampling ratio of 64 are implemented on the same die. The analog part is designed to operate at a low voltage with a low power consumption. Techniques to achieve simultaneously a high performance and a low power consumption are discussed in details. The minimum stopband attenuation of the decimator is more than 120 dB and the passband ripple of the overall converter is less than 0.0003 dB. The first decimation stage is a special tapped comb filter, whereas the remaining stages are realized without general multipliers by simultaneously implementing all the filter coefficients by using special bit-serial networks. For the integrated overall stereo converter, the power consumption and the signal-to-noise ratio are 180 mW and 97 dB (85 mW and 95 dB) for a 5 V (3 V) power supply. The circuit die area is only 4.7 mm×5.5 mm using a 1.2 μm double-poly BiCMOS process