Modeling triplet spike-timing-dependent plasticity using memristive devices

Triplet-based spike-timing-dependent plasticity (TSTDP) is an advanced synaptic plasticity rule that results in improved learning capability compared to the conventional pair-based STDP (PSTDP). The TSTDP rule can reproduce the results of many electrophysiological experiments, where the PSTDP fails. This paper proposes a novel memristive circuit that implements the TSTDP rule. The proposed circuit is designed using three voltage (flux)-driven memristors. Simulation results demonstrate that our memristive circuit induces synaptic weight changes that arise due to the timing differences among pairs and triplets of spikes. The presented memristive design is an initial step toward developing asynchronous TSTDP learning architectures using memristive devices. These architectures may facilitate the implementation of advanced large-scale neuromorphic systems with applications in real-world engineering tasks such as pattern classification.     

A memristive dual-slope A/D converter

As an emerging device, memristor has several excellent properties like changeable memristance, nonvolatility, and nanoscale. Based on complementary metal-oxide-semiconductor (CMOS) dual-slope analog-to-digital (A/D) converter, this paper proposes a memristive dual-slope A/D converter. Owing to the usage of memristor, the proposed memristive A/D converter not only has more compact circuit structure and simpler control timing than the CMOS one but also has advantages over the existing memristive conversion circuits in circuit design and application. For the memristive A/D converter, a conversion process consists of two count procedures. By means of controlling the memristance change in the two count procedures, the A/D converter converts an analog signal to the corresponding digital count value. Meanwhile, the conversion result is inferred according to the circuit structure of the A/D converter. Then, combining the conversion process and PSPICE simulation, this paper analyzes the anti-interference performance of the A/D converter. Further, the robustness of the A/D converter is presented, applying the similar analysis methods. The analysis results demonstrate that the proposed A/D converter has good anti-interference and robustness performances.     

SPICE modeling of nonlinear memristive behavior

The recent discovery of the ‘modern’ memristor has drawn great attention of both academia and industry. Given their favorable performance merits, memristors are expected to play a fundamental role in electronic industry. Modeling of memristive devices is essential for circuit design, and a number of Simulation Program with Integrated Circuit Emphasis (SPICE) models have already been introduced. The common problem in most models is that there is no threshold consideration; hence, only a few address the nonlinear nature of the device. This paper aims to present a SPICE implementation of a threshold‐type switching model of a voltage‐controlled memristive device that attributes the switching effect to a tunneling distance modulation. Threshold‐type switching is closer to the actual behavior of most experimentally realizable memristive systems, and our modeling approach addresses the issue of programming thresholds. Both the netlist and the simple schematic are provided, thus making it easy to comprehend and ready to be used. Compared with other modeling solutions, it involves significantly low‐complexity operation under an unlimited set of frequencies, and its simulation results are in good qualitative and quantitative agreement with the theoretical formulation. The proposed model is used to simulate an antiserial memristive switch, proving that it can be efficiently introduced in complex memristive circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

A generalized family of memristor‐based voltage controlled relaxation oscillator

Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage‐controlled memristor‐based relaxation oscillator including two memristors is presented. The operation of two memristors‐based voltage relaxation oscillator circuits is demonstrated theoretically with the mathematical analysis and with numerical simulations. The generalized expressions for the oscillation frequency and conditions are derived for different cases, where a closed form is introduced for each case. The effect of changing the circuit parameters on the oscillation frequency and conditions is investigated numerically. In addition, the derived equations are verified using several transient PSPICE simulations. The power consumption of each oscillator is obtained numerically and compared with its PSPICE counterpart. Furthermore, controlling the memristive oscillator with a voltage grants the design an extra degree of freedom which increases the design flexibility. The nonlinear exponential model of memristor is employed to prove the oscillation concept. As an application, two examples of voltage‐controlled memristor‐based relaxation oscillator are provided to elaborate the effect of the reference voltage on the output voltage. This voltage‐controlled memristor‐based relaxation oscillator has nano size with storage property that makes it more efficient compared with the conventional one. It would be helpful in many communication applications.     

Optical memristive switches

Optical memristive switches are particularly interesting for the use as latching optical switches, as a novel optical memory or as a digital optical switch. The optical memristive effect has recently enabled a miniaturization of optical devices far beyond of what seemed feasible. The smallest optical – or plasmonic – switch has now atomic scale and in fact is switched by moving single atoms. In this review, we summarize the development of optical memristive switches on their path from the micro- to the atomic scale. Three memristive effects that are important to the optical field are discussed in more detail. Among them are the phase transition effect, the valency change effect and the electrochemical metallization.     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

Field test and EMTP simulation of transient voltages when clearing a transformer secondary fault

A field test was carried out to investigate a fault clearing transient due to current interruption of a three‐phase to ground fault at the secondary side of a 3‐MVA, 22/6.6‐kV transformer by a vacuum circuit breaker. EMTP simulations in comparison with the measured results have made it clear that the capacitance C_p of a CR divider to measure voltages reduces dv/dt of transient recovery voltage across the circuit breaker by the ratio of (C_t/(C_t + C_p) where C_t is the transformer stray capacitance. The leakage inductance evaluated from the transformer rating has been found to be noticeably greater than that determined from the measured fault current possibly due to the transformer saturation. Considering the transformer magnetizing conductance and selecting an appropriate interrupted current, EMTP simulation gives a satisfactory result compared with a field test. © 1999 Scripta Technica, Electr Eng Jpn, 130(2): 40–48, 2000     

Modeling of dipole–dipole‐coupled,electric field‐driven,protein‐based computing architectures

In the present study, we propose a novel approach for the realization of protein‐based logic circuits potentially suitable for nanoscale digital signal processing and computing architectures. Electric field‐induced switching of Dronpa, an artificial protein, is demonstrated through simulations with the NAMD molecular dynamics simulation software, and a circuit model that describes such switching behavior is presented. Simulations suggest that digital signal propagation and the majority gate can be realized by the utilization of such proteins if they are dipole–dipole coupled and are driven by proper electric fields. Copyright © 2013 John Wiley & Sons, Ltd.     

A class of versatile circuits,made up of standard electrical components,are memristors

In this paper, we propose a whole class of memristor circuits. Each element from the class consists of the cascade connection between a static nonlinear two‐port and a dynamic one‐port. The class may be divided into two subclasses depending on the input variable (voltage or current). Within each of these subclasses, two further sets of memristor circuits may be distinguished according to which output voltage and current of the two‐port represents one of the system states. The simplest memristor circuits make only use of purely passive elementary components from circuit theory, an absolute novelty in this field of research. Thus they are suitable circuit primers for the introduction of the topic of memristors to undergraduate students. A sample circuit is built using discrete devices and its memristive nature is validated experimentally. In case the one‐port is purely passive, the proposed circuits feature volatile memristive behavior. Allowing active devices into the dynamic one‐port, non‐volatile dynamics may also emerge, as proved through concepts from the theory of nonlinear dynamics. Given the generality of the proposed class, the topology of the emulators may be adjusted so as to induce a large variety of dynamical behaviors, which may be exploited to accomplish new signal processing tasks, which conventional circuits are unable to perform. Copyright © 2015 John Wiley & Sons, Ltd.     

The stability of a chaotic PWM boost converter

A novel chaotic pulse‐width‐modulation (PWM) boost converter has been previously proposed to reduce electromagnetic interference (EMI) in DC–DC converters, where the circuit design and simulations have been conducted, but the problems such as the mean value estimation of state variables for circuit parameter design, the ripple estimation of the input current and the stability analysis have been remained to be addressed in this paper. Here, a mean value estimation method is first proposed, which is used to estimate the mean values of state variables of chaotic PWM boost converters for facilitating the circuit parameter design and selection of circuit components. Although ripples are slightly increased, caused by adopting chaotic carriers, the DC–DC converter with reduced EMI is still stable under the chaotic PWM control. This work provides a theoretic verification of the effectiveness and practicability of the proposed chaotic PWM DC–DC converters. Copyright © 2010 John Wiley & Sons, Ltd.     

Accurate substrate modelling of RF CMOS

The losses within the substrate of an RF IC can have significant effect on performance in a mixed signal application. In order to model substrate coupling accurately, it is represented by an RC network to account for both resistive and dielectric losses at high frequency (> 1 GHz). A small‐signal equivalent circuit model of an RF IC inclusive of substrate parasitic effect is analysed in terms of its y‐parameters and an extraction procedure for substrate parameters has been developed. By coupling the extracted substrate parameters along with extrinsic resistances associated with gate, source and drain, a standard BSIM3 model has been extended for RF applications. The new model exhibits a significant improvement in prediction of output reflection coefficient S₂₂ in the frequency range from 1 to 10 GHz in device mode of operation and for a low noise amplifier (LNA) at 2.4 GHz. Copyright © 2006 John Wiley & Sons, Ltd.     

Single crystalline SrTiO<Subscript>3</Subscript> as memristive model system: From materials science to neurological and psychological functions

Taking the advantage of the well-established defect chemistry of SrTiO₃, acceptor and donor doped SrTiO₃ single crystals are used as model systems to understand the roles of oxygen vacancies and the Schottky barrier in the resistive switching. More importantly, SrTiO₃ based memristive devices are used to emulate the neurological and psychological functions of the brain. The synaptic plasticity is achieved with Ni/Nb-SrTiO₃/Ti memristive devices, and the learning and forgetting processes of the brain, together with the resultant explicit and implicit memories, are also realized with the device. Associative learning, a classical learning case of the brain, is demonstrated as well. The emulation of various neurological and psychological functions in a single memristive device simplifies the construction of the artificial neural network and facilitates the advent of the artificial intelligence. In this work, materials science becomes directly related to neurology and psychology.     

Crisis‐induced coexisting multiple attractors in a second‐order nonautonomous memristive diode bridge‐based circuit

This paper reports a second‐order nonautonomous memristive diode bridge‐based circuit, upon which a system model is established. The AC and DC equilibrium points and their stability evolutions are theoretically analyzed, and the mechanisms of complex dynamical behaviors are explored in detail. Furthermore, the stimulus‐dependent dynamical behaviors are numerically performed by the single‐parameter bifurcation diagrams, Lyapunov exponents, and phase portraits. Of particular concern, it should be highly emphasized that multiple kinds of crisis scenarios associated with the initial conditions are found in a specified parameter region, resulting in that coexisting multiple attractors under different initial conditions are discovered for the fixed system parameters. Additionally, hardware experiments and PSpice circuit simulations are used to confirm the numerically simulated results.     

Global unique solvability for memristive circuit DAEs of Index 1

Known solvability results for nonlinear index‐1 differential‐algebraic equations (DAEs) are in general local and rely on the Implicit Function Theorem. In this paper, we derive a global result which guarantees unique solvability on a given time interval for a certain class of index‐1 DAEs with certain monotonicity conditions. Based on this result, we show that memristive circuit DAEs arising from the modified nodal analysis are uniquely solvable if they fulfill certain passivity and network topological conditions. Furthermore we present an error estimation for the solution with respect to perturbations on the right‐hand side and in the initial value. Copyright © 2013 John Wiley & Sons, Ltd.     

A low distortion CMOS continuous‐time common‐mode feedback circuit

In high‐gain fully differential operational amplifier (FD op‐amp) design, the output common‐mode (CM) voltage of the FD op‐amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common‐mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuous‐time CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded‐cascode op‐amp and the other is the Multiply‐by‐Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog‐to‐digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.