A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-/spl mu/A standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.     

A 4-Mbit CMOS EPROM

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.     

A 1-Mbit CMOS dynamic RAM with design-for test functions

A 1-Mb CMOS DRAM measuring 4.3/spl times/11.7 mm/SUP 2/ (50.32 mm/SUP 2/) has been fabricated using 1.0-/spl mu/m CMOS double-poly single-metal process technology. Both moat and second-level poly are clad to reduce circuit propagation delays. The chip incorporates two modes of 8-bit parallel READ/WRITE, as well as additional functions for test-time reduction. Eight 1-Mb family members can be produced by metal mask selection. The device uses static column circuitry along with two-stage intermediate output buffers to achieve a typical column address access time of 20 ns.     

An experimental 4-Mbit CMOS DRAM

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.     

A high-speed 16-kbit n-MOS random-access memory

This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of 200 ns) with low-power dissipation (600 mW at the 400-ns cycle time). The fully decoded memory is fabricated on a 5/spl times/7 mm/SUP 2/ chip and is assembled in a 22-lead ceramic dual-in-line package.     

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

A 5-V 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b dynamic RAM with a static column model and fast page mode has been built in a 0.8-/spl mu/m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10.9 /spl mu/m/SUP 2/ and requires only a 2-/spl mu/m trench to obtain a storage capacitor of 50 fF with 10-nm SiO/SUB 2/ equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C/SUB B/-to-C/SUB S/ capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300-mil dual-in-line package with performances of 90-ns RAS access time and 30-ns column address access time.     

An experimental 1 Mbit DRAM based on high S/N design

The key to achieving 1-Mb is higher signal-to-noise ratio, while maintaining single 5-V operation even for small feature-size MOSTs. To meet this requirement, three developments are proposed: a corrugated capacitor (memory) cell, a multidivided data line structure, and an on-chip voltage limiter. The results include an improvement in signal-to-noise ratio by a factor of about 22 and provision for single 5-V operation. These techniques have been proven to be useful through the design and evaluation of an experimental 21-/spl mu/m/SUP 2/-cell, single-5-V, 1-Mb NMOS DRAM. Its significant features include: an access time of 90 ns, a power dissipation of 295 mW at 260 ns cycle time, and a 46 mm/SUP 2/ chip area.     

An 18K bipolar dynamic random access memory

A 2K/spl times/9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75 ns and 300 ns access and cycle time, respectively. The design is based on a two device cell of 800 /spl mu/m/SUP 2/ size. All chip input and output signals are TTL compatible.     

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier

A 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b CMOS DRAM characterized by a twisted driveline sense-amplifier (TDSA) scheme and a multiphase drive circuit which enable faster access time and a smaller peak power supply current, respectively, is described. The implementation of an initialize mode with CAS-before-RAS (CBR) logic control, which reduces the memory-chip initialization time by almost a thousand times, is also discussed. The chip measures 6.38/spl times/17.38 mm/SUP 2/ and has been fabricated by using double-well CMOS technology with a minimum design rule of 0.8 /spl mu/m. A typical access time of 65 ns and a peak power supply current of less then 150 mA have been obtained.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A 50 ns 4K static DSA MOS RAM

An advanced DSA MOS (DMOS) technology is discussed as it applies to a high-speed 4K bit semiconductor static memory. It uses a polysilicon gate length of 4 /spl mu/m, a gate oxide thickness less than 800 /spl Aring/, and a shallow junction depth (<0.6 /spl mu/m) using conventional photolithographic methods. With these features, the effective channel length of the DSA MOST was reduced to 0.5 /spl mu/m and a smaller junction capacitance was obtained by the use of a high-resistivity (100-200 /spl Omega/.cm) substrate without a substrate bias generator. Combined with the depletion load transistors and selective oxidation processing, a static RAM of 50 ns access time at 630 mW power dissipation, die size of 5.24/spl times/5.36 mm/SUP 2/, and cell size of 53/spl times/62 /spl mu/m/SUP 2/ was obtained.     

A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology

A high-density 256-kb flash electrically erasable PROM (E/SUP 2/PROM) with a single transistor per bit has been developed by utilizing triple-polysilicon technology. As a result of achieving a novel compact cell that is as small as 8/spl times/8 /spl mu/m/SUP 2/, even with relatively conservative 2.0-/spl mu/m design rules, a small die size of 5.69/spl times/5.78 mm/SUP 2/ is realized. This flash E/SUP 2/PROM is fully pin-compatible with a 256-kb UV-EPROM without increasing the number of input pins for erasing by introducing a novel programming and erasing scheme. Programming time is as fast as 200 /spl mu/s/byte and erasing time is less than 100 ms per chip. A typical access time of 90 ns is achieved by using sense-amplifier circuitry.     

A 90 ns 256K /spl times/ 1 bit DRAM with double-level Al technology

A high-performance 256K /spl times/ 1bit DRAM with double-level Al technology is described. It has a small die size of 8.5 /spl times/ 4.0 mm/SUP 2/, an access time of 90 ns, and a soft error rate of less than 1000 FITs. The first and second Al layers are used as bit lines and word lines, respectively. Double-level Al technology is also applied to periphery circuit regions and contributes to a 15 percent reduction of die size in conjunction with a simplified sense-restore circuit. A compact memory cell (10.9 /spl times/ 6.1/spl mu/m /SUP 2/) with a storage capacitance of over 50 fF is obtained through the use of wafer stepping and dry etch techniques.     

A 200-mW GaAs 1 K SRAM with 2-ns cycle time

A very high-speed and low-power 1024/spl times/1 SRAM has been designed and fabricated using a normally-off recessed-gate FET technology. Minimum gate length is 0.7 /spl mu/m. A minimum access time of 1.4 ns has been obtained with a power dissipation of 210 mW. The memory cell area is 1197 /spl mu/m/SUP 2/ and the chip size is 1.91/spl times/2.21 mm/SUP 2/. The output voltage swing across a 50-/spl Omega/ load is 700 mV. The maximum simulated yield for 1 K SRAMs is discussed theoretically. A mean standard deviation in threshold voltage less than 15 mV is required to obtain 100% design yield. The SRAM has been shown to be fully operational using the march and checkerboard tests and exhibits read and write cycle times of 2 ns.     

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.