Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f_T) of 207 GHz and an f_MAX extrapolated from Mason's unilateral gain of 285 GHz. f_MAX extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12×2.5 μm² have these characteristics at a linear current of 1.0 mA/μm (8.3 mA/μm²). Smaller transistors (0.12×0.5 μm²) have an f_T of 180 GHz at 800 μA current. The devices have a pinched base sheet resistance of 2.5 kΩ/sq. and an open-base breakdown voltage BV_CEO of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f_T at small lateral dimensions     

Super low noise InGaP gated PHEMT

Very high performance InGaP/InGaAs/GaAs PHEMTs will be demonstrated. The fabricated InGaP gated PHEMTs devices with 0.25 × 160/cm² and 0.25 × 300 μm² of gate dimensions show 304 mA/mm and 330 mA/mm of saturation drain current at V_GS = 0 V, V_DS = 2 V, and 320 mS/mm and 302 mS/mm of extrinsic transconductances, respectively. Noise figures for 160 μm and 300 μm gate-width devices at 12 GHz are measured to be 0.46 dB with a 13 dB associated gain and 0.49 dB with a 12.85 dB associated gain, respectively. With such a high gain and low noise, the drain-to-gate breakdown voltage can be larger than 11 V. Standard deviation in the threshold voltage of 22 mV for 160 μm gate-width devices across a 4-in wafer can be achieved using a highly selective wet recess etching process. Good thermal stability of these InGaP gated PHEMTs is also presented     

A 3.3 V 32 Mb NAND flash memory with incremental step pulseprogramming scheme

While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm² die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA     

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm² die size and a 1.1 μm² effective cell size     

High frequency/high dynamic range CMOS VGA

A novel CMOS variable gain amplifier (VGA) with high frequency and high dynamic range is proposed. The VGA has a controllable gain range of -50 dB-+50 dB which can be controlled by adjusting the external voltage as well as an enhanced operating frequency range up to 200 MHz. It is fabricated using 0.35 μm CMOS technology and has a core area of 580×660 μm     

High gain operational amplifier implemented in 0.5 μm GaAs E/DHEMT technology

A high voltage gain operational amplifier implemented in 0.5 μm GaAs E/D HEMT technology is presented. The amplifier principally consists of a differential input stage and a high gain cascode stage which was developed by Toumazou and Haigh (1990). On-wafer measurement verifies that the amplifier achieves an open-loop voltage gain of 73 dB and a unity-gain bandwidth of 1.78 GHz     

Influence of buffer layer thickness on DC performance ofGaAs/AlGaAs heterojunction bipolar transistors grown on siliconsubstrates

The DC performance of GaAs/AlAs heterojunction bipolar transistors (HBTs) grown on silicon substrates with buffer layers ranging from 0 to 5 μm was investigated. Current gain, collector-emitter breakdown voltage, emitter-base and collector-base diode ideality factors, and breakdown voltages were measured as the buffer layer thickness was varied between 0 and 5 μm. The current gain steadily increases with increasing buffer layer thickness until the layer reaches 3 μm. However, the other DC parameters are relatively insensitive to the buffer layer thickness. A small-signal current gain of 60 is typically achieved for devices with 6×6-μm² emitters at a density of 6×10⁴ A/cm² when the buffer layer is ⩾3 μm     

Partially relaxed multiquantum well InGaAs/AlGaAs heterojunctionphototransistor operating at 955-970 nm

The authors report a partially relaxed InGaAs multiquantum well based heterojunction phototransistor with high responsivity in the transmission window of the GaAs substrate which shows no degradation in performance due to lattice relaxation. The peak responsivity increased from 10 A/W at 0.5 μW incident optical power to 100 A/W at 50 μW corresponding to a current gain of 925. At 8 V collector-emitter voltage the responsivity is constant from 957 to 973 nm, with a responsivity of 5 A/W at 0.5 μW and 55 A/W at 50 μW     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

High-drive CMOS current amplifier

A high-performance current amplifier is proposed which is based on a folded-cascode transresistance amplifier and a low-distortion class AB current output stage. The loop gain of the transresistance amplifier exhibits a gain bandwidth product of 10 MHz and a DC gain as high as 100 dB which allows accurate closed-loop operations to be achieved. Despite the intrinsic low-linearity performance of current amplifiers with respect to their voltage amplifier counterpart, the proposed circuit provides an output current of 7 mA with a total harmonic distortion (THD) better than -55 dB while requiring only 200 μA of quiescent current for the output transistors. The circuit was fabricated in a 1.2 μm CMOS process, uses a 5 V power supply, and dissipates 4 mW     

A high temperature precision amplifier

A precision operational amplifier has been developed for instrumentation applications in which the circuitry must operate in ambient temperatures as high as 200°C. At 200°C the amplifier maintains an input offset voltage and current of less than 200 μV and 1 nA respectively, a gain bandwidth product of 2.2 MHz, and a slew rate of 5.4 V/μS. The amplifier is fabricated in a standard CMOS process and consumes 5.5 mW of power at a supply voltage of 5 V. A continuous time auto-zeroed amplifier topology is used to achieve the low offset voltage levels. At high temperatures the leakage currents of the sample and hold switches used to achieve auto-zeroing, degrading the offset correction voltages stored on the hold capacitors. This degradation is reduced by using large external hold capacitors and by minimizing the diffusion area of the switches through the use of a doughnut shaped layout. The effect of the voltage degradation is reduced by sensing the offset correction voltage with a low sensitivity differential auxiliary input stage. A new input switch topology is used to reduce the amplifier's input offset current at high temperatures     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

Integrated amplifiers using fully ion-implanted InP JFETs with hightransconductance

Monolithically integrated amplifiers have been fabricated using JFETs with a gate length of 1.5 μm and a maximum transconductance of 110 mS/mm, the highest ever reported for ion-implanted InP JFETs. The amplifiers utilized both a conventional direct-coupled design and a new symmetrical design. The conventional direct-coupled amplifier shows a maximum gain of 8 (18 dB) while the symmetrical amplifier design exhibits the same gain without DC offset regardless of the FET threshold voltage and the power supply voltage used     

A low-voltage low-power fully-integratable automatic gain controlfor hearing instruments

A low-voltage low-power bipolar automatic gain control (AGC) for hearing instruments that works in the current domain and operates on a single 1.3-V battery is presented. In this AGC a large time constant (50 ms) is realized on-chip. The AGC consists of a gain cell, a comparator and a voltage follower. The active circuitry of the AGC has been integrated in the DIMES01 process and the total circuit demonstrates operation down to 1 V with only 4 μW power consumption. The compression range amounts to 38 dB. The AGC has a dynamic range (DR) of 62 dB at the output over a bandwidth of 10 kHz     

A novel high-gain image sensor cell based on Si p-n APD in chargestorage mode operation

A high-gain image sensor cell based on Si-avalanche p-n photodiodes in the charge-storage mode from below to above the breakdown voltage region without avalanche discharge during the readout time period is described. Photoelectron conversion characteristics of a proposed dual-gate avalanche photodiode (APD) image sensor cell in below-breakdown voltage operation were analyzed on the assumption that multiplication gain during storage time, which depends on APD bias, followed an empirical formula involving multiplication gain and reverse bias in DC bias condition. The above-breakdown voltage operation is also considered. Experimental results agree with results from analytical models     

An experimental large-capacity semiconductor file memory using16-levels/cell storage

A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3-μm CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 μs, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10^-7 h^-1)     

A 3 V 10 MHz pseudo-differential SC bandpass filter using gainenhancement replica amplifier

This paper describes the design strategy and implementation of a high frequency low voltage pseudo-differential SC filter which use opamps with gain enhancement replica amplifier. Experimental results of a biquad SC bandpass with a center frequency of 10 MHz and a Q of 10 are presented. The realized opamp has an open-loop unity-gain bandwidth of 850 MHz, a phase margin of about 62°, and a dc gain of 50 dB. The prototype filter dissipates 23 mW from a 3 V supply and occupies 0.3 mm ² in a 0.8 μm N-well single-poly, double-metal CMOS process     

A 14 ns 256 K×1 CMOS SRAM with multiple test modes

A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 μm twin-tub, single-poly, double-metal technology on p/p⁺ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1×13.7 μm² and a chip size of 3.9×9.5 mm² have been achieved     

Micromechanical fiber-optic attenuator with 3 μs response

Optomechanical fiber-optic attenuators are bulky and slow. The mechanical antireflection switch (MARS) modulator offers a high-speed alternative for applications including dynamic gain control in fiber amplifiers. This paper describes a compact electrically controlled variable attenuator using a micromechanical device where electrostatic deflection of a silicon nitride quarter-wave dielectric layer suspended over a silicon substrate creates a variable reflectivity mirror. This device is packaged with two fibers in one ceramic ferrule placed in contact with a gradient index (GRIN) collimation lens, so that the input light reflects from the modulator in the collimated beam plane and couples into the output fiber. Using a 300 μm diameter MARS attenuator and a 500 μm diameter collimation lens, the total insertion loss at 1550 nm was 3.0 dB with no applied voltage, increasing to 31 dB at 35.2 V. The polarization dependent loss was less than 0.06 dB. Full attenuation with more than 100 mW input power produced no damage. The response time was 2.8 μs to move from maximum to minimum transmission and 1.1 μs to return to maximum transmission