On the design parameters of flip-chip PBGA package assembly foroptimum solder ball reliability

An experimental investigation of the warpage of a flip-chip plastic ball grid array package assembly is presented and a critical deformation mode is identified. The experimental data, documented while cooling the assembly from the underfill curing temperature to -40°C, clearly reveal the effect of the constraints from the chip and the PCB on the global behavior of the substrate. The constraints produce an inflection point of the substrate at the edge of the chip. An experimentally verified three-dimensional (3-D) nonlinear finite element analysis proceeds to quantify the effect of the substrate behavior on the second-level solder ball strains. An extensive parametric study is conducted to identify the most critical design parameter for optimum solder ball reliability     

Material property effects on solder failure analyses

The effects of material properties modeling on the solder failure analyses by numerical simulations are studied. The packaging structure of plastic ball grid array on printed circuit board was modeled. Two different types of molding compounds and two different types of substrates were employed and combined for the plastic ball grid array package modeling. The material properties were assumed as temperature dependent elastic and viscoelastic, and finite element method was used to calculate and analyze the strain energy densities of the solder balls. The chip warpage was also studied, and related with the solder ball reliability analyses by discussing the viscoelastic characteristics of the materials and their influences on the deformations. The results showed that the warpage developments of the packaging structure showed very different behaviors, and the mechanism of the strain energy density accumulations in the solder balls were also different depending on the material properties modeling and their combinations. This study demonstrates that appropriate modeling of the material properties is critical for the interpretation and understanding the microelectronics reliability mechanisms.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.     

Thermal cycling aging effects on microstructural and mechanicalproperties of a single PBGA solder joint specimen

This paper reports on an experimental study on how thermal cycling aging exposure changes the solder joint microstructure, intermetallic layer thickness and the residual shear strength and fatigue life in a single plastic ball grid array (PBGA) solder joint specimen. The single BGA solder joint specimen was specially designed to evaluate the microstructure and mechanical properties of three different batches of solder joint after subjected to 0, 500, 1000, and 2000 cycles of thermal cycling aging (-40°C to 125°C). It is important to relate the effects of thermal cycling aging on the changes of the microstructural and intermetallic layer thickness to the residual shear strength and fatigue life of solder joints subjected to thermal cycling aging exposure. The results of this study shows that the microstructural and intermetallic development due to thermal cycling aging has a major impact on the residual mechanical and fatigue strength of the solder joint. It was noted that the solder joint shear strength and residual fatigue life degrades with exposure to thermal cycling aging     

Finite element analysis for solder ball failures in chip scale package

The failure mechanism of solder ball connect in chip scale package (CSP) utilizing wire-bonded ball grid array was elucidated using finite element analysis in this study. The macro-micro-coupling technique was used in the current model. There exist two factors which contribute to solder ball cracking: shear stress due to thermal expansion mismatch between the package and the PCB and warpage of the package itself. This study revealed that shear stress due to the thermal expansion mismatch prevailed over warpage of the package in causing the solder ball cracking in the present type of CSP.     

Finite element modeling of electronic packages subjected to drop impact

As more electronic products become portable, many product manufacturers have started to pay more attention to the robustness of their products. Finite element (FE) simulation has become increasingly popular in the analysis of products subjected to impact loading. The need for details in a FE mesh is always balanced by considerations of simulation time and available computational resources. In this paper, three commonly used approaches to FE modeling of a ball grid array (BGA) package subjected to drop impact are evaluated. The first model comprises a detailed mesh of the printed circuit board (PCB), integrated circuit (IC) package and interconnecting solder balls using solid three-dimensional (3-D) elements. The degrees of freedom is reduced for the second mesh by using shell elements for the PCB and IC package while retaining the detailed mesh of the solder balls using solid 3-D elements. The third mesh is a further simplification of the second mesh whereby the solder balls are replaced by a single beam element each. The stresses within the solder balls are then obtained in a separate FE analysis of a detailed solder ball mesh using the displacement history of nodes around the beam elements from the previous analysis as inputs. Solder ball stresses from all three meshes were found to differ by as much as 40% although PCB deflection compared favorably.     

Stability of the warpage in a PBGA package subjected to hygro-thermal loading

The CTE and CHE mismatch between materials in a thin PBGA package is primarily attributed to the warpage which occurs when the package is being mounted on to a PCB, especially when the moisture content reaches a specified value. In this paper, the stability equations for the warpage in a PBGA package without the solder balls being subjected to hygro-thermal loading, by modeling it as an initially perfect/imperfect composite plate, have been developed. The analytical closed-form solutions are found and used to compute not only the critical moisture content but also the warpage occurring before the critical loads are reached. The buckling of the PBGA package, at the solder reflow peak temperature, occurs when the theoretical moisture content reaches 0.259–0.283 wt.%. This theoretical critical moisture content accurately predicts the experimental critical moisture content (0.25–0.30 wt.%) derived from our previous work. The results, from comparison between theoretical and experimental critical moisture content, indirectly indicate that the PBGA package has little imperfection. However, the large initial imperfect structure of the package does not easily reach the buckling stage because of moisture absorption. In addition to this, the structure of the PBGA package before buckling become stress-free at the moisture level of 0.077 wt.% and at room temperature during moisture conditioning.     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

Procedure for design optimization of a T-cap flip chip package

In this study, a 1/4 three-dimensional finite element model of a T-cap flip chip package containing the substrate, underfill, solder bump, silicon die, metal cap and cap attachment was established to conduct thermo-mechanical reliability study during the flip chip fabrication processes. The applied thermal load was cooled from 183 °C to ambience 25 °C to determine the thermal stress and warpage during the curing period of solder ball mounting process. Under fixed geometry, two levels of underfill, metal caps and cap attachments were used to conduct the 2³ factorial design for determining reliable material combinations. The statistical tests revealed that the significant effects affecting the thermal stress were the underfill, metal cap, cap attachment and the interaction between the underfill and cap attachment. The metal cap, cap attachment and their interaction significantly affected the warpage. The proposed regression models were used to perform the surface response simulations and were useful in selecting suitable materials for constructing the package. This study provides a powerful strategy to help the designer to easily determine reliable packaging structures under various reliability considerations.     

Impact life prediction modeling of TFBGA packages under board level drop test

Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

Thermo-mechanical reliability analysis of a RF SiP module based on LTCC substrate

The RF SiP module based on LTCC substrate has attracted considerable attention in wireless communications for the last two decades. However, the thermo-mechanical reliability of this 3D LTCC architecture has not been well-studied as common as its traditional ceramic package structure. A practical RF SiP module based on LTCC substrate was presented and its thermo-mechanical reliability was analyzed in this paper, with emphasis on the reliability of heat reflow process, the operating state and fatigue of second-level solder joints. The configuration and assembly process of the SiP module were briefly introduced at first, and qualitative analysis was made according to the reliability problem that may occur in the manufacturing process and the operating state. Through FEM simulation, this paper studied the warpage and stress variation of the RF SiP module, as well as parametric studies of some key package dimensions. Solder joint reliability under temperature cycling condition was also analyzed in particular in this paper. The results show that for the heat reflow process and operating state, the maximum warpage is both on the top LTCC substrate, but the maximum stresses are on the outermost solder ball and the kovar column at the corner, respectively. There is a large residual stress on the critical solder ball at the end of the reflow process and the key package dimensions has little effect on it. The thickness of top LTCC substrate has a significant impact on the thermal deformation and thermal stress, followed by the height of kovar columns. The reason for the considerable thermal stress on the kovar column is the non-uniform of temperature distribution. The key to reducing thermal deformation and stress in the operating state is the employment of effective cooling measures. It is found by comparison that the reliability of critical solder joints can be greatly improved by adding suitable underfill.     

Squeegee bump technology

An innovative solder bumping technology, termed squeegee bumping, has been developed at Motorola's Interconnect Systems Laboratory that uses baked photoresist as a mask for solder printing to deposit fine pitch solder bumps on wafers. This process provides much better alignment accuracy and is capable of bumping finer pitch devices than stencil printing technology. Solder paste printing uses a screen printer similar to that used for stencil printing. Greater versatility of solder materials can be obtained through solder paste than the electroplating. Cost modeling shows that the squeegee bump technology has a significant cost benefit over controlled collapse chip connection (C4) technology. This is because the C4 process has very low efficiency in labor and materials usage. Statistical process control data show an average bump height of 118 ± 3.5 μm, and a maximum-to-minimum bump height range of 17 μm over a 150 mm-diameter wafer and have been produced repeatedly on test wafers with 210 μm peripheral pitch. A 109.6 ± 1.3 μm bump height on orthogonal array with 250 μm pitch has been successfully demonstrated with greater than 90% die yield. Bump reliability has been studied using both multiple reflows and extended thermal/humidity storage procedures. No degradation of shear strength was observed after up to 10 × reflows and 1008 h of a thermal/humidity stress environment. Bump reliability was also evaluated by assembling squeegee bumped dice on a plastic chip scale package (CSP). Liquid-to-liquid thermal shock cycling at a temperature range of -55°C to +125°C had a characteristic life of 2764 cycles with a 1st failure at 1050 cycles. No failures were observed after 432 h of autoclave stress at 121°C, 100% RH, 15 psig test condition