Direct gold and copper wires bonding on copper

The key to bonding to copper die is to ensure bond pad cleanliness and minimum oxidation during wire bonding process. This has been achieved by applying a organic coating layer to protect the copper bond pad from oxidation. During the wire bonding process, the organic coating layer is removed and a metal to metal weld is formed. This organic layer is a self-assembled monolayer. Both gold and copper wires have been wire-bonded successfully to the copper die even without prior plasma cleaning. The ball diameter for both wires are 60 μm on a 100 μm fine pitch bond pad. The effectiveness of the protection of the organic coating layer starts from the wafer dicing process up to the wire bonding process and is able to protect the bond pad for an extended period after the first round of wire bond process. In this study, oxidization of copper bond pad at different packaging processing stages, dicing and die attach curing, have been explored. The ball shear strength for both gold and copper ball bonds achieved are 5 and 6 g/mil² respectively. When subjected to high temperature storage test at 150 °C, the ball bonds formed by both gold and copper wire bond on the organic coated copper bondpad are thermally stable in ball shear strength up to a period of 1440 h. The encapsulated daisy chain test vehicle with both gold and copper wires bonding have passed 1000 cycles of thermal cycling test (−65 to 150 °C). It has been demonstrated that orientation imaging microscopy technique is able to detect early levels of oxidation on the copper bond pad. This is extremely important in characterization of the bondability of the copper bond pad surface.     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Effect of wire diameter on the thermosonic bond reliability

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.     

New observations on intermetallic compound formation in gold ball bonds: general growth patterns and identification of two forms of Au4Al

Relatively little information is available on the growth patterns and metallurgy of Au–Al intermetallics in fine-pitch (FP) and ultra-fine pitch (UFP) ball bonding. This paper presents a study of the growth pattern and chemistry of intermetallic compounds formed between a 25 μm 4 N gold wire and aluminium pad metallization after isothermal ageing in air at 175 °C. The data show the intermetallics grow vertically and laterally under the ball and totally consume the Al in the bond pad at <20 h. Then, a third layer of intermetallic grows between Au₄Al and Au₅Al₂. Measurements and observations made with EDX and optical microscopy lead to the conclusion that the new compound is a different form of Au₄Al, most probably a low-temperature version of the α-Au₄Al intermetallic structure. Electrical resistance during intermetallic growth was not measured in this study but wire chemistry and bonding conditions are found to affect the thickness of the intermetallic compounds, which suggests that the resistance of ball bonds during moulding and operation can change.     

Structural reliability assessment of multi-stack package (MSP) under high temperature storage (HTS) testing condition

Wire ball open failure at the interface of the gold wire and bonding pad of a multi-stack package (MSP) under high temperature storage (HTS) condition of 150 °C is studied. Failure analysis using FIB-SEM was conducted by in-plane moiré interferometry and FEA to clarify the failure mechanism. The ball open failure due to Kirkendall void that results from metal diffusion at high temperature was accelerated by the tensile stress imposed at the gold wire. The tensile stress developed at the gold wire when packages showing different warpage behaviours were stacked. Mechanical interaction between top and bottom packages caused unstable warpage, readily twisted and saddled. The wire came in contact with the photo-sensitive solder resist (PSR) dam because of the unstable warpage and this contact resulted in tensile stress at the gold wires. Solder flux residues reacted with the encapsulant, and as a result, the encapsulant of the top package adhered to the chip of the bottom package, and this adherence created additional tensile stress at the gold wires. To reduce the tensile stress at the wires, the PSR dam was removed, loop shape was altered from 45° to 90°, water soluble flux was applied, and cleaning process was added. HTS reliability was significantly improved and guaranteed after reducing the tensile stress at the wires.     

Wire bond loop profile development for fine pitch-long wireassembly

Die size reductions can be achieved through “optical shrinks,” compaction of existing layouts, or redesigns to finer fab geometries. For some die the limiting factors for die size reduction are bond pad pitch and bond pad size. In these “pad limited” designs, the circuitry is concentrated in the center of the die. Precious empty space exists between the bond pads in the periphery of the die and the circuitry in the die core. The only hope for die size reductions in these designs lies in advances in assembly technology that allow for reductions in bond pad pitches and bond pad size. Fine pitch assembly poses a number of challenges for conventional wire bond technology. Reducing bond pad pitch increases the probability of ball shorting, bond wire shorting, and bond wire damage. On the other hand, decreasing the die size by reducing the bond pad pitch results in longer wire lengths thus limiting some assembly options such as moving to smaller diameter bonding wires. Wire loop profile becomes a critical factor for control in fine pitch assembly. In this paper a statistical design of experiment is used in developing a wire bond loop profile control. The effect of major bonding parameters, such as kink-height, reverse loop, loop factor, wire tension, and their impact on loop profile are analyzed. The results obtained define the bond parameter requirements that must be met in order to control the wire loop profile to optimize fine pitch wire bond assembly yields     

Effect of the direct current on microstructure,tensile property and bonding strength of pure silver wires

In the microelectronics assembly and packaging industry, the wire bonding has become an important process to connect lead frames and pads. In the past, gold and copper were the main materials of wire bonding. However, the cost of gold wires is getting higher nowadays and yet wire bonding cannot be wholly replaced by copper wire; thus silver wires become a novel bonding material in recent years. The reliability test of wires was a static method; this study leads electrical current into the wires to estimate the structural changing and interface properties of Al pads (positive and negative pad). After leading 90% critical fusing current density (CFCD) into a 23 μm silver wire, some grains of silver wire had grown up and formed into equal-diameter grains (EDG). After the current test, the fracture position of bonded wires moved from heat affect zone (HAZ) of electric flame-off (EFO) to the neck of HAZ. Otherwise, the current test would reduce the tensile strength of wire. The bonding strength of the positive pad was lower than that of the negative pad. The intermetallic compound (IMC) of bonding interface was AgAl₂.     

Optimization of the Cu wire bonding process for IC assembly using Taguchi methods

The yield of IC assembly manufacturing is dependent on wire bonding. Recently, the semiconductor industry demands smaller IC designs and higher performance requirements. As such, bonding wires must be stronger, finer, and more solid. The cost of gold is continuously appreciating, and this has become a key issue in IC assembly and design. Copper wire bonding is an alternative solution to this problem. It is expected to be superior over Au wires in terms of cost, quality, and fine-pitch bonding pad design. To obtain the best wire bonding quality, we employed Taguchi methods in optimizing the Cu wire bonding process. With Cu wire bonding technology, the production yield increased from 98.5% to 99.3% and brought approximately USD 0.7 million in savings.     

Improving the deflection of wire bonds in stacked chip scale package (CSP)

The deformation of gold wire bonds during transfer molding of stacked chip scale package (CSP) can seriously cause wire crossover and shorting. The major challenges of the stacked CSP development are to reduce the wire sweep (deflection), and make the sufficient space clearance between the wires of first to second die. In this paper, M shape wire looping program is developed to increase the wire sweep resistance in the stacked CSP. Both linear elastic finite element analysis and experiments based on wire bonding and molding process evaluation are conducted. It is found that M shape looping program is much better than conventional normal wire shape in terms of wire sweep resistance after molding. X-ray and scanning electronic microscopy (SEM) can verify the improvement of wire deflection after chemical de-capsulation. It is believed that using M shape looping program can efficiently overcome the risk of wire shorting and improve the yield of wire bonds in high volume production of stacked CSP.     

Microstructure and creep behaviour of eutectic SnAg and SnAgCu solders

The paper presents creep data, that was gained on specimens of different microstructures. The three specimen types have been flip chip solder joints, pin trough hole solder joints and standard bulk solder specimens. The bulk solder specimen was a dog-bone type specimen (diameter=3 mm, LENGTH=117 mm). The pin trough hole solder joint consisted on a copper wire that was soldered into a hole of a double sided printed circuit board (thickness 1.5 mm). The flip chip solder joint specimen consisted of two silicon chips (4 mm × 4 mm), which were connected by four flip chip joints (one on each corner). SnAg and SnAgCu flip chip bumps (footprint 200 μm × 200 μm, joint height 165–200 μm, centre diameter 90…130 μm) were created by printing solder paste.Constant–load creep tests were carried out on all three specimen types at temperatures between 5 and 70 °C. Creep data was taken for strain rates between 10⁻¹⁰ and 10⁻³ s⁻¹. The specimens were tested in “as cast” condition and after thermal storage.The microstructural properties of the bulk specimens and real solder joints were examined using metallographic sectioning, optical microscopy techniques, and SEM-microprobe analysis. The results of the microstructural analysis were related to the investigated mechanical properties of the solders. Models of SnAg3.5 and SnAg4Cu0.5, that can be used with the ANSYS FEM software package, will be presented.     

Oxidation of copper pads and its influence on the quality of Au/Cu bonds during thermosonic wire bonding process

To understand the copper oxide effect on the bondability of gold wire onto a copper pad, thermosonic gold wire bonding to a copper pad was conducted at 90–200 °C under an air atmosphere. The bondability and bonding strength of the Au/Cu bonds were investigated. The bondability and bonding strength were far below the minimum requirements stated in industrial codes. At elevated bonding temperature of 200 °C, the bondability and bonding strength deteriorated mainly due to hydroxide and copper oxide formation on the copper pad. Oxide formation occurred if no appropriate oxide preventive schemes were applied. At lower bonding temperature, 90 °C, poor bondability and low bonding strength were mainly attributed to insufficient thermal energy for atomic inter-diffusion between the gold ball and copper pad.Copper pad oxidation was investigated using an electron spectroscopy for chemical analysis (ESCA) and thermogravimetric analysis (TGA). An activation energy of 35 kJ/mol for copper pad oxidation was obtained from TGA. This implies that different mechanisms govern the oxidation of copper pad and bulk copper. Hydroxide and copper oxide were identified based on the shifted binding energy. Cu(OH)₂ forms mainly on the top surface of copper pads and the underlying layer consists mainly of CuO. The hydroxide concentration increased with increasing the heating temperatures. After heating at 200 °C, the hydroxide concentration on the copper pad surface was approximately six times that at 90 °C. Protective measures such as passivation layer deposition or using shielding gas are critical for thermosonic wire bonding on chips with copper interconnects.     

Overmold technology applied to cavity down ultrafine pitch PBGApackage

The transfer molding technology is normally used for leadframe type packages and chip-up plastic ball grid array (PBGA) packages. This technology has been applied to cavity down PBGA packages where, normally, a liquid epoxy is dispensed by a needle in the cavity in order to cover the device and gold wires without exceeding the solder ball height plane. The new encapsulation approach using transfer molding process as well as the debug/qualification method and results using an ultrafine pitch wirebond PBGA process will be described     

Effects of Cu and Pd addition on Au bonding wire/Al pad interfacial reactions and bond reliability

Finer pitch wire bonding technology has been needed since chips have more and finer pitch I/Os. However, finer Au wires are more prone to Au-Al bond reliability and wire sweeping problems when molded with epoxy molding compound. One of the solutions for solving these problems is to add special alloying elements to Au bonding wires. In this study, Cu and Pd were added to Au bonding wire as alloying elements. These alloyed Au bonding wires—Au-1 wt.% Cu wire and Au-1 wt.% Pd wire—were bonded on Al pads and then subsequently aged at 175°C and 200°C. Cu and Pd additions to Au bonding wire slowed down interfacial reactions and crack formation due to the formation of a Cu-rich layer and a Pd-rich layer at the interface. Wire pull testing (WPT) after thermal aging showed that Cu and Pd addition enhanced bond reliability, and Cu was more effective for improving bond reliability than Pd. In addition, comparison between the results of observation of interfacial reactions and WPT proved that crack formation was an important factor to evaluate bond reliability.     

Effect of electronic flame off parameters on copper bonding wire: Free-air ball deformability, heat affected zone length, heat affected zone breaking force

Cu bonding wire is more and more used for interconnections to integrated circuits (ICs) to reduce cost and increase performance compared to Au wire. To eliminate underpad damage for Cu wire applications, it is worthwhile to reduce the hardness of the free-air ball (FAB). Short heat affected zone (HAZ) and high HAZ breaking load are often required for advanced microelectronics packaging in order to decrease the loop height and thereby the package thickness.Online measurements of deformability and HAZ breaking force at temperatures close to the bonding temperature of 220 °C are new tools used in this study to evaluate the effects of electronic flame off (EFO) current and firing time on the Cu FAB deformability and the HAZ length and tensile strength. FABs with 50 μm diameter formed from a 25 μm diameter Cu wire with a breaking load of 118.6 mN were used. EFO currents and firing times ranged from 40 to 250 mA and 0.11 to 0.90 ms, respectively. Average FAB deformability factors, HAZ breaking forces, and HAZ lengths were in the rounded ranges of 36.64–44.09% (with a deformation force of 0.60 N), 107.7–116.8 mN, and 167–215 μm, respectively. When produced with 250 mA current during 0.11 ms, the FABs are 7.01–7.89% more deformable than when produced with 45 mA during 0.9 ms, the HAZ breaking force is 7.53–9.37% higher, and the HAZ length is 7–90 μm shorter.     

Reduction of ultrasonic pad stress and aluminum splash in copper ball bonding

Given the cost and performance advantages associated with Cu wire, it is being increasingly seen as a candidate to replace Au wire for making interconnections in first level microelectronics packaging. A Cu ball bonding process is optimized with reduced pad stress and splash, using a 25.4 μm diameter Cu wire. For ball bonds made with conventionally optimized bond force and ultrasonic settings, the shear strength is ≈140 MPa. The amount of splash extruding out of bonded ball interface is between 10 and 12 μm. It can be reduced to 3-7 μm if accepting a shear strength reduction to 50-70 MPa. For excessive ultrasonic settings, elliptical shaped Cu bonded balls are observed, with the minor axis of the ellipse in the ultrasonic direction and the major axis perpendicular to the ultrasonic direction. To quantify the direct effect of bond force and ultrasound settings on pad stress, test pads with piezoresistive microsensors integrated next to the pad and the real-time ultrasonic force signals are used. By using a lower value of bond force combined with a reduced ultrasound level, the pad stress can be reduced by 30% while achieving an average shear strength of at least 120 MPa. These process settings also aid in reducing the amount of splash by 4.3 μm.     

A mechanism of threshold voltage changes for WNx gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN_x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN_x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.     

Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low-K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low-K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low-K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low-K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low-K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.     

A simple model for the mode I popcorn effect for IC packages

A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).     

Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs

An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm²) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm²/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.