A CMOS image sensor with light-controlled oscillating pixels for an investigative optobionic retinal prosthesis system

This paper presents a high-dynamic range CMOS image sensor architecture incorporating light-controlled oscillating pixels which can act as front-end for an investigative optobionic retinal prosthesis research effort. Each pixel acts as an independent oscillator, whose frequency is proportional to the local light intensity. A 9×9 pixel array has been fabricated in the AMS CMOS opto process. Each pixel's area amounts to , each pixel photodiode area is while the array occupies . Measured results show that the sensor can achieve a linear optical dynamic range of 80 dB (from 0.24 Hz to 2.2 kHz). Its linear electrical dynamic range exceeds 134 dB (from 100 mHz to 502 kHz). The nominal power dissipation is about 50 nW per pixel.     

Low-voltage nanopower clock generator for RFID applications

The design of an on-chip RC-based oscillator, implemented in a standard BiCMOS process, without any external component, is presented. The proposed oscillator provides a clock signal at a frequency of 50 kHz with a temperature coefficient smaller than 0.3%/^°C over a temperature range from 0 to , without any external trimming. The proposed oscillator operates with a supply voltage of 0.8 V and has a power consumption of at room temperature. The chip area is .     

A high precision low dropout regulator with nested feedback loops

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a standard CMOS process. The die area is a . The measurement results show that the total error of the output voltage caused by line and load variations is less than ±3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11 V, while the output current is 165 mA, the output load is and 20 in parallel.     

Low power impedance measurement integrated circuit for sensor applications

In this paper an integrated circuit for the measurement of the real and imaginary part of an impedance is presented. The circuit is intended for its use in a wireless integrated system. A mixed analog/digital approach has been adopted in order to minimize power and area requirements, as requested by the application. The four electrode configuration is used for impedance measurement using two excitation current sources and a buffer instead of an instrumentation amplifier, therefore reducing the circuit complexity. The digital block controls the working frequency and can compensate the phase error introduced by the analog filters, thereby reducing the total error in the measurement. The integrated circuit has been designed in a CMOS process and it works with 3.3 V with a power consumption of . Experimental results to verify its functionality are presented.     

An ultra-low power integer-N frequency synthesizer for MICS transceivers

The ultra-low power frequency synthesizer for the transceivers used in the application of Medical Implantable Communication Services (MICS) is presented. The MICS band is from 402 to 405 MHz. Each channel spacing is 300 kHz. Integer-N architecture is used to implement the frequency synthesizer. The post layout simulations show that the total power consumption of the system is less than at 1.2 V power supply. The gains of the charge pump and voltage controlled oscillator (VCO) are and 50 MHz/V, respectively. The standard 300 kHz external clock is used as the reference. The design is carried out in the IBM 90 nm 9LPRF CMOS technology.     

A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NF_min of 4.46 dB. The reverse isolation S12 of the LNA can achieve and the input and output return losses are better than . The input 1-dB compression point is and IIP3 is . This LNA drains 10 mA from the supply voltage of 1 V.     

Self-aligned In0.49Ga0.51P/GaAs HBT DC and RF characteristics related with orientations

A self-aligned InGaP/GaAs HBT DC and RF characteristics related with orientations were studied. The DC current gain was greater for the [0 1 1] emitter orientation compared to orientation. However, it also showed slightly better RF performance for orientation with a cutoff frequency f_T 69 GHz compared to the f_T of 62 GHz for the [0 1 1] orientation. This experimental work has been proposed that the dependence of the characteristics could be attributed to both piezoelectric effect and the difference between lateral etched profiles in different directions.     

A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

Porous silicon thin film as CO sensor

This work presents the electric behavior of porous silicon (PS) thin films when the material's surface is exposed to carbon monoxide. PS thin films were fabricated by the electrochemical anodization method of Si-c (1 0 0) substrates with resistivity . The samples were prepared at 20 min anodization time and anodization current. Aluminum electrodes were deposited on the surface of the material by high vacuum evaporation, such that the electric conduction was parallel to the substrate's surface. The detector was placed in vacuum during 1 h and then CO was allowed into the vacuum chamber. Measurements of the I-V characteristic were carried out at atmospheric pressure, in vacuum and with CO. Changes in the resistance of the material, of about MΩ, were observed in the different samples, indicating that the material is sensitive to the presence of CO and therefore suitable as gas sensor.     

Ionic outgassing from photoacid generators upon irradiation at 13.5 nm

Photoresist outgassing is considered a possible source of contamination of optics in extreme ultraviolet (EUV) lithography at 13.5 nm. We measured the relative proportions of ionic outgassing from 18 commercially available photoacid generators (PAG), which is a key component of chemically amplified photoresists, upon irradiation at 13.5 nm. These PAG include 17 triarylsulfonium or diaryliodonium salts, which contain or as the anion, and one PAG of molecular type. The overall outgassed ions in the range 10-200 u were counted in relative proportions. Outgassing of F⁺ is found to be dominant, and for most PAG the extent of F⁺ outgassing shows a satisfactory correlation with the ratio of F atomic photoabsorption to the overall PAG photoabsorption. Outgassed ions F⁺, CF⁺, and from PAG containing the anion and additional such as , and from those containing are identified. Triphenylsulfonium perfluoro-1-butanesulfonate is one PAG to emit the most abundant F⁺ and total ionic fragments, and a PAG of molecular type (N-hydroxy-5-norbornene-2,3-dicarboximide perfluoro-1-butanesulfonate) also emits abundantly both hydrocarbon ions and F⁺. Ionic outgassing of PAG cations includes (C₆H₅)₂S⁺ from R(C₆H₅)₂S⁺ salts and I⁺ from diaryliodonium salts. For PAG containing t-C₄H₉, significantly less F⁺ outgassing is observed; additional outgassing pathways are proposed. The pressure rise caused by PAG shows no dependence on the anion identity, but is correlated with cation photoabsorption, and ascribed to neutral aryl outgassing. Other minor outgassing species include from sulfonates; and ‘photostable’ PAH cations are identified for the first time and provide evidence of concurrent outgassing from, and polymerization of, PAG upon irradiation at 13.5 nm.     

PAMBE growth of (1 1 2¯ 2)-oriented GaN/AlN nanostructures on m-sapphire

We report on the plasma-assisted molecular-beam epitaxial growth of (1 1 2¯ 2)-oriented GaN/AlN nanostructures on (1 1¯ 0 0) m-plane sapphire. Moderate N-rich conditions enable to synthesize AlN(1 1  2) directly on m-sapphire, with in-plane epitaxial relationships [1 1 2¯ 3¯]_AlN∥[0 0 0 1]_sapphire and [1  0 0]_AlN∥[1 1 2¯ 0]_sapphire. In the case of GaN, a Ga-excess of one monolayer is necessary to achieve two-dimensional growth of GaN(1 1 2¯ 2). Applying these growth conditions, we demonstrate the synthesis of (1 1 2¯ 2)-oriented GaN/AlN quantum well structures, showing a strong reduction of the internal electric field. By interrupting the growth under vacuum after the deposition of few monolayers of GaN under slightly Ga-rich conditions, we also demonstrate the feasibility of quantum dot structures with this orientation.     

High-mobility pentacene thin-film transistors with copolymer-gate dielectric

Pentacene thin-film transistors have been obtained using polymethyl-methacrylate-co-glyciclyl-methacrylate (PMMA-GMA) as the gate dielectric. The optimum active layer thickness in thin-film transistors (OTFTs) was investigated. The present devices show a wide operation voltage range. The on/off current ratio is as high as 10⁵. In linear region (), the field-effect mobility of device increases with the increase in gate field at low-voltage region (), and a mobility of 0.33 cm²/V s can be obtained when . In saturation region, the mobility increases linearly with the gate field, and a high mobility of 1.14 cm²/V s can be obtained at . The influence of voltage on mobility of device was investigated.     

On VLSI design of rank-order filtering using DCRAM architecture

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 1P6M technology. As shown in the result of physical implementation, the core size is and the VLSI implementation of ROF can operate at 256 MHz for 1.8 V supply.     

CMOS current-mode integrating receivers for Gbytes/s parallel links

This paper presents the design of fully differential current-mode integrating receivers for Gbytes/s parallel links. Both class A and class AB configurations are considered. The proposed receivers consist of a transimpedance front-end that provides a low and tunable matching impedance to the channels to accommodate current-mode signaling, an integrating stage that acts as a low-pass filter to suppress the transient disturbances coupled to the channels and receiver, and a regenerative sense amplifier to amplify the output voltage of the preceding integrator to full swing. The class AB configured sense amplifier provide a voltage gain that is twice that of class A sense amplifier, enabling a fast sensing and latching. The proposed receiver has been implemented in UMC , 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. Simulation results demonstrate that the proposed class current-mode integrating receivers provide full output voltage swing when the data rate is 2.5 Gbyte/s.     

A very-high output impedance charge pump for low-voltage low-power PLLs

This article presents the design of a high output compliance, very-high output impedance single-ended charge pump implemented using a new low-voltage current mirror. The output current is sampled and a feedback loop forces it to be equal to the desired reference current. This results in a very-high output impedance over a very wide output voltage range, accurate Up/Down current matching, and low transient glitches. The proposed charge pump was implemented using STMicroelectronics 1-V 90-nm CMOS process. Simulations using Spectre show that the Up/Down output currents remain constant and matched within 1% over a charge pump output voltage ranging from 119 to 873 mV. Monte Carlo process variations and mismatch simulations indicate that the 1-σ standard deviation between the Up and Down current components is , or 6.8% of the nominal charge pump current at either end of the output voltage range.     

Power analysis and design of wide dynamic range CMOS imaging sensors

Wide dynamic range (WDR) CMOS imaging sensors (CIS) are being designed for new portable, implantable and sensory applications, which demand low power consumption. Compared to normal CISs, high quality WDR CISs generally consume much more power. Up to now, the power consumption of a WDR CIS has never been formally studied. This paper focuses to model and analyze the power consumption of two major WDR CIS designs. Analytical equations are derived for the WDR CIS power, and are verified with HSPICE simulations. The analysis indicates that the power consumption of WDR CISs is dominated by the column bus driving power for large imaging array, while photocurrent related power is negligible. Hence, the WDR CIS power is heavily dependent on the load of the column bus and the read-out frequency. A new partial quantization scheme is developed to acquire WDR images with greatly reduced read-out frequencies. Its power consumption is also analytically derived and verified with HSPICE simulations. A 256×256 partial quantization column consumes about 124.0 nW/pixel in the CMOS process for 16-bit dynamic range and 30 Hz frame rate. The power analysis is further verified by experimental measurements of a proof-of-concept 32×32 partial quantization imaging sensor in the CMOS process.     

Parallel links with current-mode incremental signaling and per-pin skew compensation

This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. Both the transmitter and receiver of the links are current-mode configured to utilize the intrinsic advantages of current-mode signaling. The receiver maps the direction of its channel currents representing the logic state of the incoming data to two voltages whose values are largely different, enabling a convenient recovery of both the logic state and timing information of the received current-mode data in the voltage-mode domain, and suppression of the common-mode disturbances coupled to the channels. Inter-signal timing skews are compensated by inserting a delay line in each channel whose time delay is determined by the phase difference between the transmitted master clock and the output of the recovering comparator. To assess the effectiveness of the proposed inter-signal timing skew compensation technique, a 2-bit 1 Gbytes/s parallel link has been designed in IBM- CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results of the parallel link with the proposed deskewing scheme demonstrate that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.