Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

Design optimization of high breakdown voltage AlGaN-GaN power HEMT on an insulating substrate for R/sub ON/A-V/sub B/ tradeoff characteristics

High breakdown voltage AlGaN-GaN power high-electron mobility transistors (HEMTs) on an insulating substrate were designed for the power electronics application. The field plate structure was employed for high breakdown voltage. The field plate length, the insulator thickness and AlGaN layer doping concentration were design parameters for the breakdown voltage. The optimization of the contact length and contact resistivity reduction were effective to reduce the specific on-resistance. The tradeoff characteristics between the on-resistance and the breakdown voltage can be improved by the optimization of the above design parameters, and the on-resistance can be estimated to be about 0.6 m/spl Omega//spl middot/cm/sup 2/ for the breakdown voltage of 600 V. This on-resistance is almost the same as that for the device on a conductive substrate.     

Photo-CVD SiO/sub 2/ layers on AlGaN and AlGaN-GaN MOSHFET

High-quality SiO/sub 2/ was successfully deposited onto AlGaN by photochemical vapor deposition (photo-CVD) using a D/sub 2/ lamp as the excitation source. The resulting interface state density was only 1.1 /spl times/ 10/sup 11/ cm/sup -2/eV/sup -1/, and the oxide leakage current was dominated by Poole-Frenkel emission. Compared with AlGaN-GaN metal-semiconductor HFET (MESHFETs) with similar structure, the gate leakage current is reduced by more than four orders of magnitude by using the photo-CVD oxide layer as gate oxide in AlGaN-GaN metal-oxide-semiconductor heterojunction field-effect transistors (MOSHFETs). With a 2-/spl mu/m gate, the saturated I/sub ds/, maximum g/sub m/ and gate voltage swing (GVS) of the fabricated nitride-based MOSHFET were 572 mA/mm, 68 mS/mm, and 8 V, respectively.     

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

A novel technique for fabricating high reliability trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. This technique provides a unit cell with 2.3/spl sim/2.4 /spl mu/m pitch and a channel density of 100 Mcell/in/sup 2/. Specific on-resistance is 0.36 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 43 V at a gate voltage of 10 V and 5 A source-to-drain current. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of oxide grown on a nonhydrogen annealed trench surface.     

一种阳极连接P型埋层的AlGaN/GaN肖特基二极管

在传统AlGaN/GaN肖特基二极管中,阳极漏电始终是制约器件耐压提高的一个重要因素。因此文中研究了在缓冲层中生长P型埋层并与阳极相连的AlGaN/GaN肖特基二极管结构 AC-PBL FPs SBD来抑制阳极的泄漏电流。同时,在二极管的两级均加上场板来调制该器件的表面电场分布。经过仿真验证可知,该结构的阳极关断泄漏电流得到了有效抑制,同时辅助耗尽沟道内的2DEG,扩大空间电荷区,进而提高了器件的耐压特性。该结构的击穿电压为733 V,与传统GET SBD器件相比,击穿电压提高了近3.4倍,Baliga优值提升了近11.6倍,说明该器件可以应用在电力电子线路中。     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

AlGaN/GaN MOSHEMTs With Liquid-Phase-Deposited $ hbox{TiO}_{2}$ as Gate Dielectric

$hbox{TiO}_{2}$ films deposited on GaN layers at room temperature through a simple and low-cost liquid-phase deposition (LPD) method are investigated and served as gate dielectrics in AlGaN/GaN MOSHEMTs. The electrical characteristics of the MOS structure on n-doped GaN show that the leakage current is about $hbox{1.01} times hbox{10}^{-7} hbox{A/cm}^{2}$ at 1 MV/cm and that the breakdown field is more than 6.5 MV/cm. The maximum drain current density of MOSHEMTs is higher than that of conventional HEMTs, and a wider gate voltage swing can also be observed. The maximum transconductance and threshold voltage almost maintain the same characteristics, even after inserting a dielectric layer between the gate metal and the 2DEG channel by using $ hbox{TiO}_{2}$ as a gate dielectric. The gate leakage current density is significantly improved, and the bias stress measurement shows that current collapse is much suppressed for MOSHEMTs.      

AlGaN/GaN power HFET on silicon substrate with source-via grounding (SVG) structure

We have developed a high-power AlGaN/GaN HFET fabricated on 4-in conductive Si substrate with a source-via grounding (SVG) structure. The SVG structure enables efficient chip layout and high packing density by the vertical configuration. By establishing a high-quality epitaxial technology on a Si substrate and by significantly reducing the parasitic resistance, a very low specific on-state resistance of 1.9 m/spl Omega//spl middot/cm/sup 2/ is achieved. The breakdown voltage is as high as 350 V, which is attributed to the Si substrate acting as a backside field plate. Because of reduction of the parasitic inductance, very high level of current (2.0 kA/cm/sup 2/) transients, i.e., a turn-on time of 98 ps and a turn-off time of 96 ps, are successfully measured for the first time.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Influence of surface states on the voltage robustness of AlGaN/GaN HFET power devices

In this work we discuss the influence of the donor-like surface state density (SSD) on leakage currents and the breakdown voltages of AlGaN/GaN heterostructure field-effect transistors (HFET) at high temperature reverse bias (HTRB) step stress. A method to extract charges at the surface by high voltage capacitance voltage (HV–CV) profiling of the gate–drain diode of a HFET is presented. Two samples with different surface passivation are compared. The SSD of the first sample is found to be similar to the polarization charge, whereas it is elevated by a factor of three on the second sample. The influence of the SSD on the electric field is investigated with electroluminescence (EL). The elevated SSD of the second sample engenders severe deficiencies in robustness found in the HTRB. The stress data, the simulation model and the images of EL indicate that the catastrophic failure arises in the dielectric underneath the gate field plate (GFP).     

Copper gate AlGaN/GaN HEMT with low gate leakage current

Copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current were demonstrated. For comparison, nickel/gold (Ni/Au) gate devices were also fabricated with the same process conditions except the gate metals. Comparable extrinsic transconductance was obtained for the two kinds of devices. At gate voltage of -15 V, typical gate leakage currents are found to be as low as 3.5/spl times/10/sup -8/ A for a Cu-gate device with gate length of 2 /spl mu/m and width of 50 /spl mu/m, which is much lower than that of Ni/Au-gate device. No adhesion problem occurred during these experiments. Gate resistance of Cu-gate is found to be about 60% as that of NiAu. The Schottky barrier height of Cu on n-GaN is 0.18 eV higher than that of Ni/Au obtained from Schottky diode experiments. No Cu diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. These results indicate that copper is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMT.     

930-V 170-m/spl Omega//spl middot/cm/sup 2/ lateral two-zone RESURF MOSFETs in 4H-SiC with NO annealing

The first lateral two-zone reduced surface field MOSFETs in 4H-SiC with NO annealing are reported. Interface properties of 4H-SiC-SiO/sub 2/ are improved, with inversion layer field-effect mobility increased to 25 cm/sup 2//V/spl middot/s, five times higher than that of dry reoxidation process, and with channel resistance significantly reduced. Devices are normally off with low leakage current. Threshold voltage is around 3 V. Blocking voltage of 930 V and specific on-resistance of 170 m/spl Omega//spl middot/cm/sup 2/ were obtained. Large-area devices with multifinger geometry are also demonstrated with scaled-up current. The output characteristics exhibit excellent linear and saturation regions.     

Long-wavelength In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As large-area avalanche photodiodes and arrays

Large-area (500-/spl mu/m diameter) mesa-structure In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiodes (APDs) are reported. The dark current density was /spl sim/2.5/spl times/10/sup -2/ nA//spl mu/m/sup 2/ at 90% of breakdown; low surface leakage current density (/spl sim/4.2 pA//spl mu/m) was achieved with wet chemical etching and SiO/sub 2/ passivation. An 18 /spl times/ 18 APD array with uniform distributions of breakdown voltage, dark current, and multiplication gain has also been demonstrated. The APDs in the array achieved 3-dB bandwidth of /spl sim/8 GHz at low gain and a gain-bandwidth product of /spl sim/120 GHz.     

Very high voltage operation (>330 V) with high current gain of AlGaN/GaN HBTs

N-p-n Al/sub 0.05/GaN/GaN heterojunction bipolar transistors with a common emitter operation voltage higher than 330 V have been demonstrated using selectively regrown emitters. Devices were grown by metalorganic chemical vapor deposition on sapphire substrates. The n-type emitter was grown selectively on a 100-nm-thick p-base with an 8 /spl mu/m n-collector structure using a dielectric mask. The shallow etch down to the collector mitigates damages induced in the dry etch, resulting a low leakage and a high breakdown. The graded AlGaN emitter results in a common emitter current gain of /spl sim/18 at an average collector current density of up to 1 kA/cm/sup 2/ at room temperature.     

High-performance RSD poly-Si TFTs with a new ONO gate dielectric

This paper developed a novel polycrystalline silicon (poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide-nitride-oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger Q/sub BD/, and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabricated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm/sup 2//V/spl middot/s, and an on/off current ratio exceeding 10/sup 8/.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.