Improving Behavioral IO Buffer Modeling Based on IBIS

High level behavioral modeling is widely used in lieu of low level transistor models to ascertain the behavior of input/output (IO) drivers and receivers. The input output buffer information specification (IBIS) is one of the most widely used methodologies to model IO drivers as it satisfies the basic requirements of a behavioral model such as IP protection, simple structure, fast simulation time, and reasonable accuracy. As driver technology gets increasingly complicated and rise time of input signal gets increasingly smaller, important considerations such as simultaneous switching noise (SSN) becomes a major consideration when simulating multiple IO drivers in the integrated circuit. Unfortunately, IBIS falls short of becoming a complete IO behavioral model when simulating for SSN. This paper addresses the problem by assessing what is missing in IBIS. A method is presented for compensating for the missing information by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models.      

An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35 μm CMOS process

In this paper a new operational amplifier is presented which is based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase dc-gain. This method does not limit the range of the output voltage swing. True performance of the Op-Amp in higher output voltage swings is another advantage of the proposed Op-Amp in comparison with the conventional structures. Bulk amplification and positive feedback are used to improve the Op-Amp specifications. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.35 μm CMOS technology. The HSPICE simulation confirms the theoretical estimated improvements.     

Organic Thin-Film Transistors: Part I—Compact DC Modeling

A generic analytical model for the current–voltage characteristics of organic thin-film transistors (OTFTs) is derived. Based on this generic model, a TFT compact dc model that meets the requirements for compact modeling, including for computer circuit simulators, is proposed. The models are fully symmetrical, and the TFT compact dc model covers all regimes of TFT operation—linear and saturation above threshold, subthreshold, and reverse biasing. The empirical fitting parameters are mostly eliminated from the characteristic equations. The developed models are also in close correspondence to several physical, parametric, and limiting models for current–voltage and mobility characteristics. An essential practical feature of the TFT compact dc model is that the model is both upgradable and reducible, allowing for easier implementation and modifications and also simultaneously allowing for separation of characterization techniques. This allows for systematic fitting of experimental data with large scattering in the values, but at the same time, preserving consistently the OTFT behavior in the model.      

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits

A compact add-on model is proposed to simulate the mechanism of charge trapping and release (detrapping) and its effect on the threshold voltage of MOSFET devices. The model uses implicit algebraic differential equations compatible with transient analysis in SPICE. It also shares the accuracy level of the transient analysis. A micro-model approach is used, and each trap is treated by a two-state Markov process. The normalization of trap behavior can be enabled or disabled, so that the designer can compare average trap behavior to the result of repeated Monte-Carlo simulations of a circuit. In this manner, the model can compromise between device-level modeling and circuit-level modeling. Unlike models geared towards digital circuit design, the trapping and release rates need not be constant during electrical stress. The trapping and release rates are a function of time, as they depend on the circuit state-space equations. An operational amplifier is analyzed using the new model, and the proposed approach is compared with the state of the art.     

Developing device models

Describes rapid implementation of semiconductor device models in SPICE using an MCAST compact model compiler. Device-model development is a vital component of circuit design and is traditionally a very challenging task. To overcome this challenge, it would be beneficial for model developers to use high-level behavioral language and model compilers. Implementations of MOS level-3 models and BSIMSOI models have demonstrated that this behavioral modeling approach is more efficient and practical than traditional C/FORTRAN methodologies and could save future model developers a significant amount of time and cost in implementation and maintenance. With the further enhancement and wider acceptance of this new approach, it is expected to promote more and better device models in the near future.     

Simulation of LED based luminaires by using multi-domain compact models of LEDs and compact thermal models of their thermal environment

Fast and accurate prediction of hot lumens of LEDs installed in luminaires is an important step in the design of robust and reliable products. A possible approach to this is to create a multi-domain circuit model of a complete LED chip + package + luminaire system that can be simulated by any Spice-like circuit simulator with electro-thermal capabilities. Many LED chip and LED package models and modeling techniques have been published recently, but compact thermal modeling of luminaires as multi heat-source system was not yet dealt with in the literature. This paper aims to fill this gap be describing a systematic approach for system (luminaire) level analysis aimed at solving the combined thermal, electrical and light output simulation problem consistently by describing a method for creating a compact thermal model of LED luminaries with an approach borrowed from the layout based electro-thermal simulation of analog ICs. The applicability of the described method is demonstrated with a real life example, including the validation of the results with thermal measurements.     

Microwave FinFET modeling based on artificial neural networks including lossy silicon substrate

Nowadays, FinFET represents a new and promising transistor structure for the aggressive downscaling of the CMOS technology. Typically, the small-signal modeling for FinFET is based on compact models or on equivalent circuit representations. As an alternative to such approaches, a small-signal behavioral model based on artificial neural networks is developed in this paper. Particular attention is devoted to modeling the low-frequency kinks of the scattering parameters, due to the lossy silicon substrate. The model is efficient and accurate, as confirmed by the comparison between measured and simulated microwave behavior.     

Small signal equivalent circuit modeling of resonant converters

A general analytical procedure is presented for the equivalent circuit modeling of resonant converters, using the series and parallel resonant converters as examples. The switched tank elements of a resonant converter are modeled by a lumped parameter equivalent circuit. The tank element circuit model consists, in general, of discrete energy states, but may be approximated by a low-frequency continuous time model. These equivalent circuit models completely characterize the terminal behavior of the converters and are solvable for any transfer function or impedance of interest. With the approximate model it is possible to predict the lumped parameter poles and zeros, and to quickly determine the relevant DC gains of the output impedance and the control to output transfer function. Closed-form solutions are given for the equivalent circuit models of both converter examples. Experimental verification is presented for the control-to-output transfer functions of both series and parallel resonant converters, and good agreement between theoretical prediction and experimental measurement is obtained     

A low-voltage low-power instrumentation amplifier based on supply current sensing technique

In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.     

MODELLA-a new physics-based compact model for lateral p-n-ptransistors

A lateral p-n-p compact model, suitable for computer-aided circuit design purposes, is introduced. In this formulation, called MODELLA, the equivalent circuit topology, analytical equations, and model parameters are derived directly from the physics and structure of the lateral p-n-p. MODELLA incorporates current crowding effects, substrate effects, and a bias-dependent output conductance and it uses the approach to lateral p-n-p high injection modeling whereby the main currents and charges are independently related to bias-dependent minority-carrier concentrations. Model-specific aspects of the parameter determination strategy are discussed; the Ning-Tang resistance determination method, for example, is shown to be highly suitable for lateral p-n-p devices. The effectiveness of this strategy and the improved performance of this physics-based formulation become evident in comparisons between MODELLA and the standard SPICE Gummel-Poon model using measured device characteristics     

具有视网膜仿生处理功能的CMOS图像传感器

借鉴生物视网膜进行图像采集和处理的结构及功能,设计了具有视网膜仿生片上信号处理电路的智能CMOS图像传感器(CIS)。像元内的仿生处理电路主要由自适应光接受器、滤波网络和减法运算电路3部分构成;CIS采用结构简单的空间滤波电阻网络和基于运算放大器的减法电路分别模拟水平细胞和双极细胞的功能,实现图像的边缘检测。在Chartered 0.35μm 2P4M CMOS工艺参数下,对各单元电路及6×6 CIS阵列进行仿真。     

Analytical Models for Architecture-Based Software Reliability Prediction: A Unification Framework

Traditional approaches to software reliability modeling are black box-based; that is, the software system is considered as a whole, and only its interactions with the outside world are modeled without looking into its internal structure. The black box approach is adequate to characterize the reliability of monolithic, custom, built-to-specification software applications. However, with the widespread use of object oriented systems design & development, the use of component-based software development is on the rise. Software systems are developed in a heterogeneous (multiple teams in different environments) fashion, and hence it may be inappropriate to model the overall failure process of such systems using one of the several software reliability growth models (black box approach). Predicting the reliability of a software system based on its architecture, and the failure behavior of its components, is thus essential. Most of the research efforts in predicting the reliability of a software system based on its architecture have been focused on developing analytical or state-based models. However, the development of state-based models has been mostly ad hoc with little or no effort devoted towards establishing a unifying framework which compares & contrasts these models. Also, to the best of our knowledge, no attempt has been made to offer an insight into how these models might be applied to real software applications. This paper proposes a unifying framework for state-based models for architecture-based software reliability prediction. The state-based models we consider are the ones in which application architecture is represented either as a discrete time Markov chain (DTMC), or a continuous time Markov chain (CTMC). We illustrate the DTMC-based, and CTMC-based models using examples. A detailed discussion of how the parameters of each model may be estimated, and the life cycle phases when the model may be applied is also provided     

Simultaneous switching noise analysis using application specific device modeling

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and /spl alpha/-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.     

Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gate-coupling behaviour

A novel modular strategy for highly flexible modeling of ESD-capable MOS compact models is introduced. This high current MOS model comprises the important gate-coupling effect and an approximated formulation for the avalanche multiplication factor. This enormously enhances the computation stability and performance of the model. An easy but accurate parameter extraction procedure based upon the model equations is described. Measurement and simulation of an application example employing the new ESD-model within a CMOS output driver exhibit the relevance of dynamic gate-coupling for the ESD-reliability of the circuit.     

A complete small-signal equivalent circuit model of cooled butterfly-type 2.5 Gbps DFB laser modules and its application to improve high frequency characteristics

A small-signal equivalent circuit model of 2.5 Gbps DFB laser modules with butterfly-type dual-in-line packages has been proposed and verified using extracted parameters. Parameters related to the equivalent circuit have been extracted from measured S parameters using the modified two-port black box model. This model includes small-signal equivalent circuits of components used for 2.5 Gbps DFB laser modules such as DFB laser, coplanar waveguides, matching resistor, bonding wires, and thermoelectric cooler (TEC). From this equivalent circuit modeling, we show that calculated frequency characteristics of DFB lasers on submount and complete DFB laser modules are similar to their measured frequency characteristics, respectively. Based on this equivalent circuit model, we propose and demonstrate a method that can improve frequency characteristics of 2.5 Gbps DFB laser modules through both experiments and simulations.     

Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

As very large scale integration (VLSI) circuit speeds and density continue to increase, the need to accurately model the effects of three-dimensional (3-D) interconnects has become essential for reliable chip and system design and verification. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative that they be kept compact without compromising accuracy, and also retain relevant physical properties of the original system, such as passivity. In this paper, we describe an approach to generate accurate, compact, and guaranteed passive models of RLC interconnects and packaging structures. The procedure is based on a partial element equivalent circuit (PEEC)-like approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior. The resulting formulation, based on nodal or mixed nodal and mesh analysis, enables the application of existing model order reduction techniques. Compactness and passivity of the model are then ensured with a two-step reduction procedure where Krylov-subspace moment-matching methods are followed by a recently proposed, nearly optimal, passive truncated balanced realization-like algorithm. The proposed approach was used for extracting passive models for several industrial examples, whose accuracy was validated both in the frequency domain as well as against measured time-domain data.     

3-D FEM Modeling and Fabrication of Circular Photonic Crystal Microcavity

In this paper, we study an unconventional kind of quasi-three-dimensional (3-D) photonic crystal (PhC) with circular lattice pattern: it consists of air holes in a GaAs material $({rm n}=3.408)$ along circular concentric lines. This particular PhC geometry has peculiar behavior if compared with the traditional square and triangular lattices, but it is difficult to model by using conventional numerical approaches such as wave expansion method. The resonance and the radiation aspects are analyzed by the 3-D finite-element method (FEM). The model, based on a scattering matrix approach, considers the cavity resonance frequency and evaluates the input–output relationship by enclosing the photonic crystal slab (PhCS) in a black box in order to define the responses at different input–output ports. The scattering matrix method gives important information about the frequency responses of the passive 3-D crystal in the 3-D spatial domain. A high sensitivity of the scattering parameters to the variation of the geometrical imperfection is also observed. The model is completed by the quality factor (Q-factor) estimation. We fabricated the designed circular photonic crystal over a slab membrane waveguide embedding InAs/GaAs quantum dots emitting around 1.28 $mu{hbox{m}}$. Good agreement between numerical and experimental results was found, thus validating the 3-D FEM full-wave investigation.      

Physics-based minority charge and transit time modeling for bipolartransistors

It has been well known for many years that the transit time model used in the SPICE Gummel-Poon model (SGPM) is not adequate for reliable design of circuits operating either at high current densities (including quasi-saturation), which is often the case in high-speed integrated circuits, or at low voltages, which is important for low-power applications. In addition, extraction of the SGPM's transit time model parameters is often very difficult and time consuming. Although various proposals for modeling the transit time were published in the past, most of them are not suited for compact transistor models required in circuit simulation from a numerical, parameter extraction and lateral scaling point of view. In this paper, a set of minority charge and transit time equations is derived which are physics-based and laterally scaleable as well as suitable for incorporation into compact models. Experimental results of the new model are presented in terms of transit time and transit frequency versus bias (I_C, V_CE), geometry, and temperature, showing excellent agreement for different types of silicon homojunction bipolar transistors