Threshold Voltage Shift Due to Mechanical Stress-Enhanced Plasma Process-Induced Damage in 0.13-μm pMOSFET

Mechanical stress-enhanced plasma process-induced damage (PPID) in 0.13-mum pMOSFET was investigated. The PPID, which was initially charged neutral, became positively charged during hydrogen annealing, thus, changing the PMOS threshold voltage (V_th). Different device structures were designed to evaluate the mechanical stress effects on PPID. The features of these positive charges, including the PPID induced V_th shift, and its channel length dependence were also investigated     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

Effects of electron and neutron irradiation on the electrical properties of Si on MgO·Al2O3 spinel

The effects of electron and neutron irradiation on the electrical conductivity and Hall coefficient of n-type heteroepitaxial (Epi) Si/spinel have been measured and compared to those for bulk vacuum-floating-zone (VFZ) silicon. A smaller degradation rate is observed for conductivity in Epi than in VFZ Si under irradiation. This effect is primarily due to a smaller mobility in Epi compared to VFZ Si, rather than to a lower defect production rate in Epi Si. Epi and VFZ Si exhibit similar carrier removal rates under irradiation, similar relative effects of electron and neutron damage, and similar annealing characteristics below 200°C which include the temperature for vacancy-phosphorus defect annealing. These similarities imply that a major fraction of the irradiation-induced defects are the same in irradiated Epi and VFZ Si at room temperature, even though extensive disorder in the “as grown” Epi Si drastically affects the pre-irradiation mobility. Thus, the inherent initial disorder in heteroepitaxial Si films does not necessarily increase radiation tolerance.     

Radiation damage in N+-implanted ZnSe

The radiation damage in 200 keV N⁺ -ion implanted (111) single crystalline ZnSe has been studied as a function of dosage and annealing treatment using cross-sectional transmission electron microscope techniques. For dosages less than 10¹⁴ /cm² no observable damage is present at room temperature or after annealing at 700°C for one hour. For a dosage 10¹⁵/cm² the radiation damage is observable at room temperature and on annealing the initial high density of small black dot defects form Frank loops which on growing still further form prismatic vacancy type loops. For dosages of 10¹⁷/cm² a very high concentration of defects form at room temperature although the material remains single crystalline. On annealing at 700°C dodecahedron voids form in the damage region and cause swelling of ? 1%. The stresses induced by this swelling is accommodated by dislocations of the a/2 <110> type which glide in from the surface on the {111} slip planes. The distribution of the radiation damage for all the dosages and on annealing up to 700°C is Gaussian with a peak coinciding with the projected range of N⁺ -ions in ZnSe as predicted by the Lindhard, Scharff and Schiot (LSS) theory. Auger depth profiling on 10¹⁷ N -ions/cm² implanted ZnSe revealed no nitrogen in the damage zone of either the as implanted (R.T.) ZnSe or those annealed at 700°C.     

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

In this letter, we investigate the effects of process-induced strain on negative bias temperature instability (NBTI) by performing a comparative study of devices with and without process-induced strain for poly-Si/SiON gate stacks. Devices with SiGe source/drain with different processing sequences and devices with a combination of SiGe S/D and compressive contact etch stop layer (CESL) were studied and compared to reference devices. We decouple the effect of processing conditions in order to ensure a correct interpretation of the results. In contrast with the previous reports, which did not consider the impact of processing conditions, this letter demonstrates that, when initial threshold voltage differences are taken into account and comparisons are performed at the same oxide electric field, no significant degradation of intrinsic NBTI behavior is found for devices with a process-induced strain. In addition, we performed an Arrhenius study showing similar activation energies for devices with and without process-induced strain, suggesting similar degradation mechanism. The results indicate that process-induced strain does not create favorable conditions for additional interface state creation     

Transient annealing of defects in irradiated silicon devices

The annealing of radiation-produced defects in semiconductor devices is discussed briefly for⁶⁰Co gamma-ray and 1-MeV electron damage, and in detail for fast-neutron damage. The effects on the reordering processes of varying the material parameters and the irradiation conditions are considered. Transient annealing of neutron damage near room temperature has been investigated for a wide variety of devices, and the data are presented in generalized form to increase their usefulness to device and circuit designers. Based on the experimental results, physical models are suggested for the reordering processes which occur during the annealing of neutron damage. Electron density is shown to be the most important factor governing the rate of transient annealing. Annealing factors are estimated for very early times (1 µs) following neutron exposure. Suggestions are made to minimize the effects of transient annealing on devices.     

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si/sub 1-y/C/sub y/ incorporation

We have demonstrated the fabrication of n/sup +/-p gated diodes using low-temperature annealing of 700/spl deg/C for 30 s with a significantly reduced junction leakage current. This is achieved with the incorporation of an epitaxially grown Si/sub 1-y/C/sub y/(y=0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950/spl deg/C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter.     

Anomalous junction leakage current induced by STI dislocations andits impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction     

Application of focused ion beam techniques and transmission electron microscopy to thin-film transistor failure analysis

The locations of process-induced defects in hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs), which are used as elements of active-matrix liquid crystal displays, were investigated by combining focused ion beam techniques with cross-sectional transmission electron microscopy (X-TEM). The FIB technique is applied to TFT failure analysis problems, which require considerable localised etching without inducing mechanical stress or damage at fragile failure locations. We demonstrate the manner in which these techniques are used to characterise TFT defects such as pinholes and portions of the multilayer damaged by mechanical stress. A dramatic improvement brought about by the FIB technique is the increase in temporal efficiency of sample preparations. X-TEM observations also lead to identification of the fault and analysis of its cause, which in turn lead to a marked yield improvement.     

Transformation of nonradiative recombination centers in GaAs/AlGaAs quantum well structures upon treatment in a CF4 plasma followed by low-temperature annealing

The influence of low-temperature annealing on the photoluminescence of GaAs/AlGaAs single-quantum-well structures treated in a low-energy CF₄ plasma is investigated. It is established that annealing at 160–300 °C causes a decrease of the photoluminescence intensity of the quantum wells located in the near-surface region, while annealing at 350–450 °C leads to partial restoration of their photoluminescence. The activation energy for the diffusion of plasma-produced point defects and the activation energy for the annealing of these defects are determined. These energies are equal to 150 and 540 meV, respectively. It is discovered that the photoluminescence of the quantum wells near the substrate, which had a low intensity in the as-grown sample, increases after treatment in the plasma and decreases after subsequent annealing monotonically with increasing annealing temperature. Repeated treatment in a CF₄ plasma leads to a repeated increase in the photoluminescence intensity of these quantum wells. It is theorized that the defects induced by the CF₄ plasma form complexes with defects introduced during growth and that these complexes are not recombination centers. After low-temperature annealing, the complexes dissociate, and the nonradiative recombination centers are recreated. Fiz. Tekh. Poluprovodn. 32, 1450–1455 (December 1998)     

Electro-optic effect in proton exchanged LiNbO3 andLiTaO3 waveguides

Electro-optic properties of proton-exchanged (PE) waveguide layers in LiTaO₃ and LiNbO₃ are studied and related to their optical characteristics. The proton-exchange process induces a degradation of the electro-optic activity in both types of waveguides, PE LiNbO₃ and PE LiTaO₃. The measured electro-optic effect is close to the detection sensitivity even when the exchange regime is performed at low temperatures for short periods of time. The PE samples have been annealed (APE waveguides) and the changes of their r₃₃ electro-optic coefficient has been followed at successively higher temperatures and periods of time. Subjected to annealing at temperatures between 265-420°C, the LiTaO₃ layers show a partially recovered r₃₃ coefficient, the recovering being different for quick and slow cooling of the samples. In thin APE LiNbO₃ waveguiding layers a restoration of r₃₃ up to 75% of the bulk value is observed due to the annealing at temperatures between 200-340°C     

Impact of the Ge Content on the Bandgap-Narrowing Induced Leakage Current of Recessed $hbox{Si}_{1 - x}hbox{Ge}_{x}$ Source/Drain Junctions

The purpose of this paper is to evaluate the impact of process-induced stress on the generation current of fully strained Si_1- xGex source/drain junctions. The Ge content of the compressively strained SiGe epitaxial layer plays a key role in the tensile stress levels present in the underlying Si substrate. Current-voltage (I-V) measurements were employed to further investigate the leakage current enhancement due to the stress-induced bandgap narrowing in the Si depletion region, when no extended defects are formed. An empirical approach is proposed to describe the Ge content dependence of the bandgap-shrinkage-induced leakage current. An increase of the intrinsic carrier concentration as a function of the stress mismatch is observed. Moreover, the role of the epilayer thickness in the generation current is also discussed.     

质子辐照对场板AlGaN／GaN HEMT器件电特性的影响

分别采用3MeV和10MeV的质子对GaN基HEMT（High Electron Mobility Transistor）器件进行辐照。实验发现：低注量辐照引起了体材料载流子浓度增加,高注量辐照引起了HEMT器件漏电流下降,跨导减小,阈值电压显著退化的结果。通过分析发现辐射感生受主缺陷引起的2DEG浓度降低是上述器件退化的主要原因。此外基于实验结果,采用辐射感生受主缺陷退化模型仿真并计算了HEMT器件主要参数随受主浓度的退化规律,仿真结果与实验结果有较好的一致性。本文实验结果也表明场板结构和SiN钝化层有效地阻止了电子陷落在表面态中,屏蔽了绝大部分的辐照损伤,是很有效的辐射加固手段。     

退火温度对Au/Ti/4H-SiC肖特基接触特性的影响

采用电子束蒸发法在4H-SiC表面制备了Ti/Au肖特基电极,研究了退火温度对Au/Ti/4H-SiC肖特基接触电学特性的影响.对比分析了不同退火温度下样品的电流密度-电压(J-V)和电容-电压(C-V)特性曲线,实验结果表明退火温度为500℃时Au/Ti/4H-SiC肖特基势垒高度最大,在.J-V测试和C-V测试中分别达到0.933 eV和1.447 eV,且获得理想因子最小值为1.053,反向泄漏电流密度也实现了最小值1.97×10-8 A/cm2,击穿电压达到最大值660 V.对退火温度为500℃的Au/Ti/4H-SiC样品进行J-V变温测试.测试结果表明,随着测试温度的升高,肖特基势垒高度不断升高而理想因子不断减小,说明肖特基接触界面仍然存在缺陷或者横向不均匀性,高温下的测试进一步证明肖特基接触界面还有很大的改善空间.     

Doping and processing epitaxial GexSi1−x films on Si(100) by ion implantation for Si-based heterojunction devices applications

The question of whether one can effectively dope or process epitaxial Si(100)/GeSi heterostructures by ion implantation for the fabrication of Si-based heterojunction devices is experimentally investigated. Results that cover several differention species (B, C, Si, P, Ge, As, BF₂, and Sb), doses (10¹³ to 10¹⁶/cm²), implantation temperatures (room temperature to 150°C), as well as annealing techniques (steady-state and rapid thermal annealing) are included in this minireview, and the data are compared with those available in the literature whenever possible. Implantation-induced damage and strain and their annealing behavior for both strained and relaxed GeSi are measured and contrasted with those in Si and Ge. The damage and strain generated in pseudomorphic GeSi by room-temperature implantation are considerably higher than the values interpolated from those of Si and Ge. Implantation at slightly elevated substrate temperatures (e.g., 100°C) can very effectively suppress the implantation-induced damage and strain in GeSi. The fractions of electrically active dopants in both Si and GeSi are measured and compared for several doses and under various annealing conditions. Solid-phase epitaxial regrowth of GeSi amorphized by implantation has also been studied and compared with regrowth in Si and Ge. For the case of metastable epi-GeSi amorphized by implantation, the pseudomorphic strain in the regrown GeSi is always lost and the layer contains a high density of defects, which is very different from the clean regrowth of Si(100). Solid-phase epitaxy, however, facilitates the activation of dopants in both GeSi and Si, irrespective of the annealing techniques used. For metastable GeSi films that are not amorphized by implantation, rapid thermal annealing is shown to outperform steady-state annealing for the preservation of pseudomorphic strain and the activation of dopants. In general, defects generated by ion implantation can enhance the strain relaxation process of strained GeSi during post-implantation annealing. The processing window that is optimized for ion-implanted Si, therefore, has to be modified considerably for ion-implanted GeSi. However, with these modifications, the mature ion implantation technology can be used to effectively dope and process Si/GeSi heterostructures for device applications. Possible impacts of implantation-induced damage on the reliability of Si/GeSi heterojunction devices are briefly discussed.     

氢离子注入法提高InAsP/InP应变多量子阱发光特性

采用气态源分子束外延系统生长了InAsP/InP应变多量子阱,研究了H 注入对量子阱光致发光谱的影响以及高温快速退火对离子注入后的量子阱发光谱的影响.发现采用较低H 注入能量(剂量)时,量子阱发光强度得到增强;随着H 注入能量(剂量)的增大,量子阱发光强度随之减小.H 注入过程中,部分隧穿H 会湮灭掉量子阱结构界面缺陷,同时H 也会对量子阱结构带来损伤,两者的竞争影响量子阱发光强度的变化.高温快速退火处理后,离子注入后的量子阱样品发光峰位在低温10K相对于未注入样品发生蓝移,蓝移量随着H 注入能量或剂量的增大而增加.退火过程中缺陷扩散以及缺陷扩散导致的阱层和垒层之间不同元素互混是量子阱发光峰位蓝移的原因.     

Ion beam milling-induced damage in AlGaAs/GaAs/AlGaAs single quantum well

Ion beam milling-induced damage in a 500 AA AlGaAs/40 AA GaAs/500 AA AlGaAs single quantum well structure was investigated using low temperature cathodoluminescence spectroscopy. The ion beam energy (500-1500 eV) dependence of luminescence intensity indicated that minimum damage is introduced at a beam energy of 500 eV. Most (80-85%) of the original luminescence intensity was recovered on annealing at 400 degrees C for 5 min.<>     

Degradation and recovery of AlGaAs/GaAs p-HEMT irradiated by high-energy particle

Results of an extensive study on the irradiation damage and its recovery behavior resulting from thermal annealing in AlGaAs/GaAs pseudomorphic high electron mobility transistors (HEMTs) subjected to a 220-MeV carbon, 1-MeV electrons and 1-MeV fast neutrons are presented. The drain current and effective mobility decrease after irradiation, while the threshold voltage increases in positive direction. The decrease of the drain current and mobility is thought to be due to the scattering of channel electrons with the induced lattice defects and also to the decrease of the electron density in the two dimensional electron gas region. Isochronal thermal annealing shows that the device performance degraded by the irradiation recovers. The decreased drain current for output characteristics recovers by 75% of pre-rad value after 300°C thermal annealing for AlGaAs HEMTs irradiated by carbon particles with a fluence of 1×10¹² cm⁻². The influence of the materials and radiation source on the degradation is also discussed with respect to the nonionizing energy loss. Those are mainly attributed to the difference of particle mass and the probability of nuclear collision for the formation of lattice defect in Si-doped AlGaAs donor layer. A comparison is also made with results obtained on irradiated InGaP/InGaAs p-HEMTs in order to investigate the effect of the constituent atom. The damage coefficient of AlGaAs HEMTs is also about one order greater than that of InGaP HEMTs for the same radiation source. The materials and radiation source dependence of performance degradation is mainly thought to be attributed to the difference of mass and the possibility of nuclear collision for the formation of lattice defects in Si-doped donor layer.     

Silicon power device material problems

The limitations imposed on the performance of large-area p-n junction devices by the size and quality of the silicon material are reviewed. It is shown that material quality problems--such as nouniform resistivity, foreign particulate matter, microdefects, dissolved oxygen, and various crystallographic defects--represent real limitations on device performance and yields; however, the effects of process-induced defects--such as diffusion- or stress-induced dislocations, diffusant precipitation, heavy metal precipitation, and interface degradation--often obscure, or even overwhelm, the effects of the grown-in defects. The importance of the interaction of process-induced defects with grown-in defects, and particularly the interaction of heavy metals with defects, foreign particulate matter and dissolved oxygen, has been emphasized by the results of recent investigations. The need for defect-free processing techniques in obtaining information on the effects of grown-in defects is discussed. Representative studies of the effects of defects on device performance are listed. New techniques for studying defects are reviewed with reference to results of interest to silicon device technology. Some growth techniques which may be helpful in eliminating certain material quality problems are discussed briefly.     

The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.