Nonlinear analysis of GaN MESFETs with Volterra series using large-signal models including trapping effects

Nonlinearities in GaN MESFETs are reported using a large-signal physics-based model. The model accounts for the observed current collapse to determine the frequency dispersion of output resistance and transconductance. Calculated f/sub T/ and f/sub max/ of a 0.8 /spl mu/m/spl times/150 /spl mu/m GaN MESFET are 6.5 and 13 GHz, respectively, which are in close agreement with their measured values of 6 and 14 GHz, respectively. A Volterra-series technique is used to calculate size and frequency-dependent nonlinearities. For a 1.5 /spl mu/m/spl times/150 /spl mu/m FET operating at 1 GHz, the 1 dB compression point and output-referred third-order intercept point are 16.3 and 22.2 dBm, respectively. At the same frequency, the corresponding quantities are 19.6 and 30.5 dBm for a. 0.6 /spl mu/m/spl times/150 /spl mu/m FET. Similar improvements in third-order intermodulation for shorter gatelength devices are observed.     

A GaN differential oscillator with improved harmonic performance

The first AlGaN/GaN HEMT based differential oscillator is reported. The MMIC oscillates at a frequency of 4.16 GHz and provides 22.9 dBm of power from one side at a biasing of V/sub gs/-1 V and V/sub ds/20 V. The HEMTs each have a 0.7 /spl mu/m/spl times/200 /spl mu/m gate. The second harmonic is 45 dB below the carrier and the third harmonic is more than 70 dB below the carrier. To our knowledge, this is the best reported harmonic performance for a GaN oscillator. The oscillator efficiency is between 4% and 9.4% depending on bias. The measured phase noise is -86.3 dBc and -115.7 dBc at offsets of 100 kHz and 1 MHz respectively. The phase noise at a 1 MHz offset is similar to the noise performance of FET based differential oscillators in other technologies.     

A temperature-dependent nonlinear analysis of GaN/AlGaN HEMTs usingVolterra series

Gain and intermodulation distortion of an AlGaN/GaN device operating at RF have been analyzed using a general Volterra series representation. The circuit model to represent the GaN FET is obtained from a physics-based analysis. Theoretical current-voltage characteristics are in excellent agreement with the experimental data. For a 1 μm×500 μm Al_0.15Ga_0.85N/GaN FET, the calculated output power, power-added efficiency, and gain are 25 dBm, 13%, and 10.1 dB, respectively, at 15-dBm input power, and are in excellent agreement with experimental data. The output referred third-order intercept point (OIP₃) is 39.9 dBm at 350 K and 33 dBm at 650 K. These are in agreement with the simulated results from Cadence, which are 39.34 and 35.7 dBm, respectively. At 3 GHz, third-order intermodulation distortion IM₃ for 10-dBm output power is -72 dB at 300 K and -56 dB at 600 K. At 300 K, IM₃ is -66 dB at 5 GHz and -51 dB at 10 GHz. For the same frequencies, IM ₃ increases to -49.3 and -40 dB, respectively, at 600 K     

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.     

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).     

应用于WiFi6的新型高线性度功率放大器设计

针对WiFi 6的设备需求,设计了一款工作在5.15 GHz～5.85 GHz的高线性度砷化镓异质结双极型晶体管射频功率放大器。为了保证大信号和高温下功率管静态工作点的稳定性,采用了一种新型有源自适应偏置电路。对射频功率检测电路进行了设计和改进,有效降低了射频系统的功耗。针对各次谐波分量产生的影响,对输出匹配网络进行了优化。仿真结果表明：该射频功率放大器芯片小信号增益达到了32.6 dB;在中心频率5.5 GHz时1 dB压缩点功率为30.4 dBm,功率附加效率超过27.9%;输出功率为26 dBm时,三阶交调失真低于-40 dBc。实测数据表明：小信号增益大于31.4 dB;5.5 GHz时1 dB压缩点功率为29.06 dBm;输出功率为26 dBm时,三阶交调失真低于-30 dBc。当输出功率为20 dBm时,二次三次谐波抑制到-30 dBc和-45 dBc。     

A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers

A nonlinear capacitance-compensation technique is developed to help improve the linearity of CMOS class-AB power amplifiers. The method involves placing a PMOS device alongside the NMOS device that works as the amplifying unit, such that the overall capacitance seen at the amplifier input is a constant, thus improving linearity. The technique is developed with the help of computer simulations and Volterra analysis. A prototype two-stage amplifier employing the scheme is fabricated using a 0.5-/spl mu/m CMOS process, and the measurements show that an improvement of approximately 8 dB in both two-tone intermodulation distortion (IM3) and adjacent-channel leakage power (ACP1) is obtained for a wide range of output power. The linearized amplifier exhibits an ACP1 of -35 dBc at the designed output power of 24 dBm, with a power-added efficiency of 29% and a gain of 23.9 dB, demonstrating the potential utility of the design approach for 3GPP WCDMA applications.     

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.     

Plug-in type 1.3-/spl mu/m fiber amplifier module for rack-mounted shelves

We have successfully developed a plug-in type PDFA module for rack mounted shelves which is assembled on a printed-board. In this module, we use a newly developed Pr/sup 3+/-doped high-NA PbF/sub 2//InF/sub 3/-based fluoride fiber and wavelength stabilized 1.017-/spl mu/m laser diodes (LDs). We have obtained a small-signal gain of 24 dB and a noise figure of 6.6 dB at 1.30 /spl mu/m with an LD drive current of 240 mA/spl times/2. We achieved an output power of 10 dBm with a signal input power of 0 dBm. The total power consumption of this module, including that of a Peltier cooler, was 3.5 W when the LD drive current was 240 mA/spl times/2.     

Highly linear 0.18-/spl mu/m CMOS power amplifier with deep n-Well structure

The linearity of a 0.18-/spl mu/m CMOS power amplifier (PA) is improved by adopting a deep n-well (DNW). To find the reason for the improvement, bias dependent nonlinear parameters of the test devices are extracted from a small-signal model and a Volterra series analysis for an optimized nMOS PA with a proper matching circuit is carried out. From the analysis, it is revealed that the DNW of the nMOS lowers the harmonic distortion generated from the intrinsic gate-source capacitance (C/sub gs/), which is the dominant nonlinear source, and partially from drain junction capacitance (C/sub jd/). Single-ended and differential PAs for 2.45-GHz WLAN are designed and fabricated using a 0.18-/spl mu/m standard CMOS process. The single-ended PA with the DNW improves IMD3 and IMD5 about 5 dB with identical power performances, i.e., 20 dBm of P/sub out/, 18.7 dB of power gain and 31% of power-added efficiency (PAE) at P/sub 1dB/. The IMD3 and IMD5 are below -40 dBc and -47dBc, respectively. The differential PA with the DNW also shows about 7 dB improvements of IMD3 and IMD5 with 20.2 dBm of P/sub out/, 18.9 dB of power gain and 35% of PAE at P/sub 1dB/. The IMD3 and IMD5 are below -45 dB and -57 dBc, respectively. These performances of the linear PAs are state-of-the-art results.     

A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-/spl mu/m CMOS

A highly integrated 2-GHz, 0.13-/spl mu/m CMOS direct-conversion transmitter for wide-band code division multiple access (WCDMA) is described. Different circuit and calibration techniques are presented that successfully suppress the carrier leakage and enable the direct-upconversion architecture to meet all WCDMA specifications. The transmitter delivers +2.5 dBm output power while consuming only 45 mA from its nominal 1.5-V supply. The overall gain can be programmed in 1-dB steps over a 100-dB range with 0.4 dB accuracy. The transmitter achieves an OIP3 of +19.3 dBm, an error vector magnitude of 4.3%, and an adjacent channel leakage ratio of -38 dBc. The measured output noise of -146 dBm/Hz in the DCS Rx band and -149 dBm/Hz in the UMTS Rx band is sufficiently low to provide an option to increase the integration level even further by eliminating the external Tx interstage filter between the power amplifier and its driver.     

Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications

A 0.25-/spl mu/m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 /spl mu/m/spl times/ 2450 /spl mu/m chip area.     

Output power density of 5.1/mm at 18 GHz with an AlGaN/GaN HEMT on Si substrate

Microwave frequency capabilities of AlGaN/GaN high electron mobility transistors (HEMTs) on high resistive silicon (111) substrate for power applications are demonstrated in this letter. A maximum dc current density of 1 A/mm and an extrinsic current gain cutoff frequency (F/sub T/) of 50 GHz are achieved for a 0.25 /spl mu/m gate length device. Pulsed and large signal measurements show the good quality of the epilayer and the device processing. The trapping phenomena are minimized and consequently an output power density of 5.1 W/mm is reached at 18 GHz on a 2/spl times/50/spl times/0.25 /spl mu/m/sup 2/ HEMT with a power gain of 9.1dB.     

基于GaN HEMT的高线性星载Doherty功率放大器设计北大核心CSCD

在射频通信链路中,功率放大器决定了发射通道的线性、效率等关键指标。卫星通信由于是电池供电,对功率放大器的工作效率要求比较高。文章基于GaN HEMT晶体管采用对称设计完成了一款高效率的Doherty功率放大器。测试结果表明:该Doherty功放的功率增益大于29 dB;1 dB压缩点功率(P_(1 dB))大于35 dBm;在35 dBm输出时,其功率附加效率(PAE)大于47.5%,三阶交调失真(IMD3)大于35 dBc;在功率回退3 dB时,其PAE大于37%,IMD3大于32 dBc。     

A physics-based frequency dispersion model of GaN MESFETs

A physics-based model for GaN MESFETs is developed to determine the frequency dispersion of output resistance and transconductance due to traps. The equivalent circuit parameters are obtained by considering the physical mechanisms for current collapse and the associated trap dynamics. Detrapping time extracted from drain-lag measurements are 1.55 and 58.42 s indicating trap levels at 0.69 and 0.79 eV, respectively. The dispersion frequency is in the range of megahertz at elevated temperature, where a typical GaN power device may operate, although at room temperature it may be few hertz. For a 1.5 /spl times/ 150 /spl mu/m GaN MESFET with drain and gate biases of 10 V and -1 V, respectively, 5% decrease in transconductance and 62% decrease in output resistance at radio frequencies (RFs) from their DC values are observed. The dispersion characteristics are found to be bias dependent. A significant decrease in transconductance is observed when the device operates in the region where detrapping is significant. As gate bias approaches toward cutoff, the difference between output resistance at dc and that at RF increases. For drain and gate biases of 10 and -5 V, output resistance decreases from 60.2 k/spl Omega/ at dc to 7.5 k/spl Omega/ at RF for a 1.5 /spl mu/m /spl times/ 150 GaN MESFET.     

Ultra-low-power 2.4 GHz image-rejection low-noise amplifier

An ultra-low-power image-rejection low-noise amplifier (IR-LNA) for 2.4 GHz ZigBee applications based on 0.18 /spl mu/m CMOS technology is presented. By using the third-order active notch filter the proposed IR-LNA can achieve high image-rejection ratio. Measurements show 12 dB gain, 1.8 dB noise figure, 38 dB image-rejection, -3 dBm input third-order intercept point, -18 and -19 dB input and output return loss while dissipating 0.6 mA from a supply voltage of 1.5 V.     

30-GHz-band over 5-W power performance of short-channel AlGaN/GaN heterojunction FETs

This paper describes the small-signal characterization through delay-time analysis and high-power operation of the Ka-band of AlGaN/GaN heterojunction field-effect transistors (FETs). An FET with a gatewidth of 100 /spl mu/m and a gate length of 0.09 /spl mu/m has exhibited a current gain cutoff frequency (f/sub T/) of 81 GHz, a maximum frequency of oscillation (fmax) of 187 GHz, and a maximum stable gain of 10.5 dB at 30 GHz (8.3 dB at 60 GHz). Delay-time analysis has demonstrated channel electron velocities of 1.50/spl times/10/sup 7/ to 1.75/spl times/10/sup 7/ cm/s in a gate-length range of 0.09-0.25 /spl mu/m. State-of-the-art performance-saturated power of 5.8 W with a linear gain of 9.2 dB and a power-added efficiency of 43.2%-has been achieved at 30 GHz using a single chip having a gatewidth of 1.0 mm and a gate length of 0.25 /spl mu/m.     

A direct conversion receiver with an IP2 calibrator for CDMA/PCS/GPS/AMPS applications

A second-order intercept point (IP2) calibration technique is developed using common-mode feedback (CMFB) circuitry in a direct-conversion receiver for wireless CDMA/PCS/GPS/AMPS applications. The IP2 calibrator is capable of providing different CMFB gain to tune its common-mode output impedance for each of the positive and negative mixer outputs. The CDMA mixer applying this method achieved a second-order input intercept point (IIP2) of 64 dBm, a third-order input intercept point (IIP3) of 4 dBm, a noise figure of 6.5 dB and a voltage gain of 42.2 dB. This result shows a 20 dB improvement from an uncalibrated IIP2 of 44 dBm. The receiver RFIC is implemented in a 0.5-/spl mu/m SiGe BiCMOS process, and it operates from a 2.7 to 3.1 V single power supply.     

A dual-b and RF front-end of direct conversion receiver for wireless CDMA cellular phones with GPS capability

A highly integrated direct conversion receiver for cellular code division multiple access (CDMA) and GPS applications is successfully developed using a 0.5-/spl mu/m SiGe BiCMOS technology. The receiver consists of two low-noise amplifiers (LNAs), a dual-band mixer, two voltage-controlled oscillators (VCOs), a local-oscillator signal generation block, and channel filters. The CDMA LNA achieves a noise figure of 1.3 dB, an input-referred third-order intercept point (IIP3) of 10.9 dBm, and a gain of 15.3 dB with a current consumption of 9.8 mA in the high-gain mode. The mixer for the CDMA mode achieves an uncalibrated input-referred second-order intercept point of 53.7 dBm, an IIP3 of 6.4 dBm, a noise figure of 7.2 dB and a voltage gain of 37.2 dB. The phase noise of the CDMA VCO is approximately -133 dBc/Hz at a 900-kHz offset from a 1.762-GHz operating frequency. It exceeds all the CDMA requirements when tested on a handset.     

Power results at 4 GHz of AlGaN/GaN HEMTs on high resistive silicon [111] substrate

The high potential at microwave frequencies of AlGaN/GaN high electron mobility transistors (HEMTs) on high resistive silicon [111] substrate for power applications has been demonstrated in this letter. For the first time, an output power density close to 1.8 W/mm and an associated power added efficiency of 32% have been measured on a 2 /spl times/ 50 /spl times/ 0.5 /spl mu/m/sup 2/ HEMT with a linear power gain of 16 dB. These results constitute the state of the art.