Hot embossing of micrographic elements in polypropylene

Micrographic features generated by electron beam lithography have been hot embossed in biaxially-oriented polypropylene (BOPP). Each micrographic element consisted of a sub-field of 30 × 30 μm with a specific configuration of symbols, lettering and graphics. The micrographic elements were integrated with arrays of diffractive gratings in the form of an optically variable device. A high quality embossing of various micrographic elements has been demonstrated in features with a linewidth dimension ?365 nm and depth ?255 nm. The replication of arrays of micrographic elements was achieved uniformly over an area of 20 × 20 mm in the BOPP film by embossing at a temperature of 130 °C.     

Pattern replication in polypropylene films by hot embossing

The hot embossing of electron beam generated structures with linewidths of 0.35-3.25 μm has been examined in biaxially-oriented polypropylene (BOPP). The individual test elements consisted of pixels of 30 × 30 μm containing a specific configuration of symbols and lettering. The embossing of these features has been performed as a function of temperature (80-140 °C) and applied pressure (2-20 kPa). Significant increases in both embossed depth and sidewall angle were evident over the temperature range 100-130 °C with a leveling off at higher temperatures attributed to the onset of a regime of viscous liquid flow. At temperatures within this regime, a critical level of pressure was required to fill the mold features. Accurate embossing of medium and coarse lettering (0.50-0.65 μm linewidth) and geometric symbols (1.25-3.25 μm linewidth) has been demonstrated at a temperature of 130 °C and an applied pressure ?13 kPa. The depth of the finest lettering (0.35 μm linewidth) was incompletely embossed under these conditions.     

Printing via hot embossing of optically variable images in thermoplastic acrylic lacquer

A novel printing process via hot embossing of either grating or micro-mirror microstructures has been demonstrated in thermoplastic acrylic lacquer. Embossing experiments were performed in the temperature range 100-150 °C and at 80 kN force. The range of microstructures has included a dot-matrix hologram, grating-based optically variable devices (OVDs) and a micro-mirror based OVD. High quality replicas of each type of device have been fabricated using this process. Embossed replicas of grating-based OVDs have shown optical effects including image switching and color movement. For devices based on micro-mirror arrays, the embossed replicas have shown an optically variable switch between a portrait and a non-portrait image. Printing via an embossing process offers the possibility of incorporating optically variable devices into documents without the use of hot stamping foil. This is particularly relevant for documents based on polymeric substrates such as credit cards and polymer banknotes.     

Circuital modelling of S-shape removal in the current–voltage characteristic of TiOx inverted organic solar cells through white-light soaking

In this work light activation phenomenon in inverted bulk heterojunction (BHJ) organic solar cells (OSC) has been electrically modelled with a two-diode equivalent circuit. OSC are based on poly(3-hexylthiophene) (P3HT): 1-(3-methoxycarbonyl)-propyl-1-1-phenyl-(6,6) C61 (PCBM) with a titanium oxide (TiO_x) sublayer. Current–voltage (I–V) characteristics show a highly pronounced S-shape that is gradually removed during light activation process. The circuit used to model I–V curves includes two diodes in forward and reverse bias together with two parallel resistances, R_P1 and R_P2. The parallel of the reverse bias diode and its corresponding resistance R_P2 models the electrical behaviour of the TiO_x interlayer. This interlayer has been thermally treated at different temperatures, from 80 °C up to 180 °C, reducing the activation time from 400 s for unbaked devices down to 30 s for devices annealed at temperatures higher than 80 °C. The S-shape shown in the I–V characteristic is completely removed after a few minutes of white-light illumination. I–V curves recorded during the activation process have been fitted with the analytical solution of the two-diode circuit based on W-Lambert function. A decrease of the subcircuit 2 equivalent resistance has been found to be the cause of S-shape removal. This resistance diminishing is in good agreement with the increase of TiO_x conductance with baking temperature and white-light exposure time found by other authors.     

A 1.25 Gbps DC-coupled laser diode driver with VBE compensation technique

A 1.25 Gbps integrated laser diode driver (LDD) driving an edge-emitting laser has been designed and fabricated in 0.35 μm BiCMOS technology. The IC can provide independent bias current (5-100 mA) with automatic power control, and modulation current (4-85 mA) with temperature compensation adjustments to minimize the variation in extinction ratio. This paper proposed an unique modulation output driver configuration which is capable of DC-coupling a laser to the driver at +3.3 V supply voltage; and combined a V_BE compensation circuit, the IC can operate at a wide temperature range (−40 to 85 °C) for date rates up to 1.25 Gbps. V_BE compensation technique is used to compensate for variation in V_BE over the operating temperature range so as to minimize the variations in rise and fall time of modulation output over temperatures.     

Low-temperature embossing technique for fabrication of large-area polymeric microlens array with supercritical carbon dioxide

This study reports an effective process for low temperature replication of polymeric microlens array using carbon dioxide (CO₂) as softening solvent and then as embossing pressure. Supercritical CO₂ is employed to soften the surface of polymer substrate and then apply pressure on it. Accordingly, microlens can be formed on the polymer substrate at low temperature. Using gas as embossing pressure can provide uniform pressure for large-area replication. During the embossing process, an array of convex microlenses is generated by partial protrusion of the substrate into the micro-holes of the mold under the action of embossing pressure and surface tension. The uniformity of large-area fabrication and optical property of the fabricated refractive microlens array on a 260 mm × 110 mm poly (methyl methacrylate) (PMMA) substrate have been verified. Little residual stress can be observed by polariscope. With the proposed method, the large-area embossing can be performed without heating and cooling. Moreover, the problems of non-uniform pressure and residual stress can be overcome.     

High thermal stability AlGaAs/InGaAs enhancement-mode pHEMT using palladium-gate technology

The dc, flicker noise, power, and temperature dependence of AlGaAs/InGaAs enhancement-mode pseudomorphic high electron mobility transistors (E-pHEMTs) were investigated using palladium (Pd)-gate technology. Although the conventional platinum (Pt)-buried gate has a high metal work function, which is beneficial for increasing the Schottky barrier height of the E-pHEMT, the high rate of intermixing of the Pt-GaAs interface owing to the effect of the continuous production of PtAs₂ on the device influenced the threshold voltage (V_th) and transconductance (g_m) at high temperatures or over the long-term operation. Variations in these parameters make Pt-gate E-pHEMT-related circuits impractical. Furthermore, a PtAs₂ interlayer caused a serious gate leakage current and unstable Schottky barrier height. This study presents the Pd-GaAs Schottky contact because Pd, an inert material with high work function of 5.12 eV. Stable Pd inhibited the less diffusion at high temperatures and simultaneously suppressed device flicker noise. The V_th of Pd/Ti/Au Schottky gate E-pHEMT was 0.183 V and this value shifted to 0.296 V after annealing at 200 °C. However, the V_th shifted from 0.084 to 0.231 V after annealing of the Pt/Ti/Au Schottky gate E-pHEMT because the Pt sunk into a deeper channel. The slope of the curve of power gain cutoff frequency (f_max) as a function of temperature was −5.76 × 10⁻² GHz/°C for a Pd/Ti/Au-gate E-pHEMT; it was −9.17 × 10⁻² GHz/°C for a Pt/Ti/Au-gate E-pHEMT. The slight variation in the dc and radio-frequency characteristics of the Pd/Ti/Au-gate E-pHEMT at temperatures from 0 to 100 °C revealed that the Pd-GaAs interface has great potential for high power transistors.     

Frequency and temperature dependent dielectric properties of Al/Si3N4/p-Si(1 0 0) MIS structure

The dielectric properties of Al/Si₃N₄/p-Si(1 0 0) MIS structure were studied from the C-V and G-V measurements in the frequency range of 1 kHz to 1 MHz and temperature range of 80-300 K. Experimental results shows that the ε′ and ε″ are found to decrease with increasing frequency while the value of ε′ and ε″ increase with increasing temperature, especially, above 160 K. As typical values, the dielectric constant ε′ and dielectric loss ε″ have the values of 7.49, 1.03 at 1 kHz, and only 0.9, 0.02 at 1 MHz, respectively. The ac electrical conductivity (σ_ac) increases with both increasing frequency and temperature. The activation energy of 24 meV was calculated from Arrhenius plot at 1 MHz. The results indicate that the interfacial polarization can be more easily occurred at low frequencies and high temperatures.     

Temperature-dependent current-voltage characteristics of Cr/n-GaAs Schottky diodes

The Cr/n-GaAs/In Schottky contacts have been formed using dc magnetron sputtering. The current-voltage (I-V) characteristics of the device have been measured by steps of 20 K in the temperature range of 60-320 K. The ideality factor n of the device has remained about unchanged between 1.04 and 1.10 and Schottky barrier height around 0.58-0.60 eV from 320 K down to 160 K. It can be said that the experimental I-V data are almost independent of temperature above 160 K. After 160 K, the n value increased with a decrease in temperature and become 1.99 at 60 K. The I-V characteristics at high temperatures have been exactly explained by the standard TE model. The nature and origin of abnormal behaviors at low temperatures have been successfully explained by the current flow through the low SBH circular patches suggested by Tung and used by some studies in literature. It has been seen that the straight line of the nT vs. T plot with a T₀ value of 14 K was parallel to that of the ideal Schottky contact. Again, a lateral homogeneous BH value of 0.62 eV was calculated from the linear relationship between the ideality factor and barrier height values. It has been seen that he ?(T = 0) and BH temperature coefficient α values obtained from the flat band BH and the Norde’s model plots are in close agreement with each other.     

Barrier height temperature coefficient in ideal Ti/n-GaAs Schottky contacts

We have measured the I-V characteristics of Ti/n-GaAs Schottky barrier diodes (SBDs) in the temperature range of 60-320 K by the steps of 20 K. The SBDs have been prepared by magnetron DC sputtering. The ideality factor n of the device has remained almost unchanged between 1.02 and 1.04 from 120 to 320 K, and 1.10 at 100 K. Therefore, it has been said that the experimental I-V data are almost independent of the sample temperature and quite well obey the thermionic emission (TE) model at temperatures above 100 K. Furthermore, the barrier height (BH) Φ_b0 slightly increased with a decrease in temperature, 320-120 K. The Φ_b0 versus temperature plot from intercepts of the forward-bias ln I versus V curves has given a BH temperature coefficient of α = −0.090 meV/K. The Norde’s function has been easily carried out to determine the temperature-dependent series resistance values because the TE current dominates in the I-V characteristics. Therefore, the Φ_b0 versus temperature plot from the Norde’s function has also given a BH temperature coefficient value of α = −0.089 meV/K. Thus, the negligible temperature dependence or BH temperature coefficient close to zero has been attributed to interface defects responsible for the pinning of the Fermi level because their ionization entropy is only weakly dependent on the temperature.     

Fabrication and characterisation of high quality ZnO thin films by reactive electron beam evaporation technique

High quality zinc oxide thin films have been deposited on silicon substrates by reactive e-beam evaporation in an oxygen environment. The effect of the growth temperature and air annealing on the structural, optical and electrical properties has been investigated. X-ray diffraction measurements have shown that ZnO films are highly c-axis-oriented and that the linewidth of the (002) peak is sensitive to the variation of substrate temperature. The optimum growth temperature has been observed at 300 °C. Raman spectroscopy has been found to be an efficient tool to evaluate the residual stress in the as-grown ZnO films from the position of the E₂ (high) mode. On the other hand, the vanishing of the 574 cm⁻¹. Raman feature after annealing has been explained as due to an increase of grain size and the reduction of O-vacancy and Zn interstitial. The SEM images have shown that the surfaces of the electron beam evaporated ZnO became smoother for the growth temperatures higher than 300 °C. The optical transmittance is the highest at 300 °C and has been increased after annealing in air showing an improvement of the optical quality. Finally, the maximum electrical resistivity has been found at 300 °C, which explains its relation with the crystal quality and increased from 5.8×10⁻² Ω cm to reach an approximate value of 10⁹ Ω cm after annealing at 750 °C.     

LP-MOCVD growth of ternary BxGa1−xAs epilayers on (0 0 1)GaAs substrates using TEB, TMGa and AsH3

Zinc-blende B_xGa_1−xAs alloys have been successfully grown on exactly oriented (0 0 1)GaAs substrates using triethylboron, trimethylgallium and arsine sources. The growth has been accomplished in a vertical low-pressure metalorganic chemical vapor deposition (LP-MOCVD) reactor. Boron incorporation behaviors have been extensively studied as a function of growth temperature and gas-phase boron mole fraction. The evolution of surface morphology was also observed.The maximum boron composition of 5.8% is obtained at the optimum growth temperature of 580 °C. RMS roughness over the surface area of 1×1 μm² is only 0.17 nm at such growth conditions. Based on the experimental results, it has been clearly shown that boron incorporation will decrease significantly at higher temperature (>610 °C) or at much lower temperature (?550 °C).     

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09 V to 0.36 V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600 °C, 700 °C and 800 °C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, D_it has a value of 2.663 × 10¹² cm⁻²/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the I_ds degradation (5.75 × 10⁻¹ mA/mm K⁻¹) for operation from 77 K to 300 K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as V_GS–V_th, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.     

Optically variable watermark (OVW) microstructures for transparent substrates

We report on the novel fabrication of optically variable watermarks (OVW) in a transparent substrate. The OVW is incorporated into the substrate via an embossing process. The master embossing die is produced by a combination of electron beam lithography, greytone photolithography, and precision electroplating techniques. The micro-embossing into polypropylene film is performed at 130 °C and 100 kN, a similar pressure to that used in intaglio printing. The optical effect produced by the device corresponds to a switch from one image to another as the device is observed in transmission when held in front of a light source and moved up and down. The image switching mechanism is a result of the refraction of the incident light through the embossed interlaced rows of micro-prisms, with the two different images corresponding to opposite prism slopes. Specific results reported here include an OVW image switch from a “$” to a “50” symbol and a second test image corresponding to an image switch from a portrait to a logo style image. Applications of the OVW technology include anti-counterfeiting protection for polymer banknotes, identity cards with transparent regions and labels attached to brand name products.     

A flip-chip packaged 80-nm In0.7Ga0.3As MHEMT for millimeter-wave low-noise applications

In this paper, we present a flip-chip 80-nm In_0.7Ga_0.3As MHEMT device on an alumina (Al₂O₃) substrate with very little decay on device RF performance up to 60 GHz. After package, the device exhibited high I_DS = 435 mA/mm at V_DS = 1.5 V, high g_m = 930 mS/mm at V_DS = 1.3 V, the measured gain was 7.5 dB and the minimum noise figure (NF_min) was 2.5 dB at 60 GHz. As compared to the bare chip, the packaged device exhibited very small degradation in performance. The result shows that with proper design of the matching circuits and packaging materials, the flip-chip technology can be used for discrete low noise FET package up to millimeter-wave range.     

High performance TaYOx-based MIM capacitors

TaYO_x-based metal-insulator-metal (MIM) capacitors with excellent electrical properties have been fabricated. Ultra-thin TaYO_x films in the thickness range of 15-30 nm (EOT ∼ 2.4-4.7 nm) were deposited on Au/SiO₂ (100 nm)/Si (100) structures by rf-magnetron co-sputtering of Ta₂O₅ and Y₂O₃ targets. TaYO_x layers were characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray (EDX) and X-ray diffraction (XRD) to examine the composition and crystallinity. An atomic percentage of Ta:Y = 58.32:41.67 was confirmed from the EDX analysis while XRD revealed an amorphous phase (up to 500 °C) during rapid thermal annealing. Besides, a high capacitance density of ∼3.7-5.4 fF/μm² at 10 kHz (ε_r ∼ 21), a low value of VCC (voltage coefficients of capacitance, α and β) have been achieved. Also, a highly stable temperature coefficient of capacitance, TCC has been obtained. Capacitance degradation phenomena in TaYO_x-based MIM capacitors under constant current stressing (CCS at 20 nA) have been studied. It is observed that degradation depends strongly on the dielectric thickness and a dielectric breakdown voltage of 3-5 MV/cm was found for TaYO_x films. The maximum energy storage density was estimated to be ∼5.69 J/cm³. Post deposition annealing (PDA) in O₂ ambient at 400 °C has been performed and further improvement in device reliability and electrical performances has been achieved.     

Dielectric spectroscopy studies on (PVP + PVA) polyblend film

The thermal behavior of (PVP + PVA) polyblend film have been examined using differential scanning calorimetry and scanning electron microscopy. Capacitance and loss tangent values of polyvinyl pyrrolidone (PVP) + polyvinyl alcohol (PVA) polyblend film were measured in the frequency range 1-100 kHz and temperature range 298-423 K. Dielectric permittivity of real part (ε′) was obtained from capacitance data and dielectric permittivity of imaginary part (ε″) was obtained from real part of dielectric permittivity and loss tangent values. The decrease in dielectric permittivity was observed with increasing frequency and also observed increase in dielectric permittivity with increasing temperature. The complex dielectric constant (ε*) has been described by the electric modulus M* = (1/ε*) = M′ + iM″. The data of M* has been analysed by the stretched exponential decay of the electric field, Φ(t) = exp−(t/τ₀)^β.     

Characterisation of titanium disilicide thin films

Properties of TiN/TiSi₂ thin films prepared on phosphorus-doped Si (1 0 0) substrates by sputtering of Ti film followed by a rapid thermal annealing in NH₃ atmosphere at different conditions were studied. Thickness of as-deposited Ti layers was 40 and 60 nm and the annealing duration was set to 10 s at temperatures from 750 to 900 °C. Formation of a compact TiN/TiSi₂/Si structure by rapid thermal annealing has been analysed by Auger electron spectroscopy and time-of-flight secondary ion mass spectroscopy depth profiling. Different amounts of oxygen in TiN layers and phosphorus redistribution in both TiN and TiSi₂ layers have also been detected. Both C54 and C49 TiSi₂ phases were identified by micro-Raman spectroscopy in samples annealed at 750 °C, whereas single C54 phase has been observed in samples annealed at higher temperatures. Creation of TiSi₂ grains of sub-micrometer size at the TiSi₂/Si substrate, explaining the depth dependence of the sheet resistance of silicide layers has been revealed by the scanning electron microscopy.     

InAs/AlSb HEMTs for cryogenic LNAs at ultra-low power dissipation

Properties of the InAs/AlSb high electron mobility transistor, essential for the design of a cryogenic low-noise amplifier (LNA) operating at low power dissipation, have been studied. Upon cooling from 300 K to 77 K, the dc transconductance g_m was enhanced by 30% at a drain-source voltage V_DS of 0.1 V. The gate current leakage showed a strong reduction of the Schottky current component at 77 K. Compared to 300 K, the cut-off frequency f_T and maximum oscillation frequency f_max showed a significant improvement at 77 K with a peak f_T (f_max) of 167 (142) GHz at V_DS = 0.2 V. The suitability of the Sb HEMT for a cryogenic LNA design up to 50 GHz, operating at low dc power dissipation, was investigated through the extraction of the NF_tot,min figure of merit. It was found that the best device performance in terms of noise and gain is achieved at a low V_DS of 0.16 V resulting in a minimum NF_tot,min of 0.6 dB for a frequency of 10 GHz when operating at 77 K. A benchmarking between the Sb HEMT and an InP HEMT has been conducted highlighting the device improvement in noise and gain required to reach today’s state-of-the-art cryogenic LNAs.     

SrO capping effect for La2O3/Ce-silicate gate dielectrics

The chemical bonding states and electrical characteristics of SrO capped La₂O₃/CeO_x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5 nm has been demonstrated. A strongly degraded effective electron mobility of 78 cm²/V s at 1 MV/cm has been obtained, which fit well with the general trend in small EOT range below 1 nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling.