An SOI-DRAM with wide operating voltage range by CMOS/SIMOXtechnology

An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc=3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80°C is longer than 20 s (Vcc=3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's     

Digital calibration technique for highly linear wide dynamic range CMOS imaging sensor

A novel digital calibration scheme is developed to improve the linearity of a wide dynamic range (DR) CMOS imaging sensor, with a low calibration overhead. Experimental results show that the distortion of the fabricated imaging sensor reaches -75.6-dB over the 95.3-dB DR after calibration.     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.     

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

The authors present a parametric model which covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel-length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.     

一种低功耗线性范围宽的跨导放大器及其在滤波器中的应用

本文分析了以往文献中提出的各类跨导放大器(OTA,operational transconductor amplifier)的结构特点,为了能更好地改善线性度并降低功耗,本文提出了一种全差分带电流负反馈的跨导放大器。在1.5V的电源电压下,经cadence仿真平台验证,该跨导放大器的线性范围拓宽到1V,IIP3达到24.80dBm,功耗低于14μW。将此跨导放大器应用到三阶椭圆低通跨导电容(OTA-C)滤波器中,经cadence仿真验证,该滤波器的幅频特性陡峭,IIP3达到13.51dBm,功耗为1.6mW。     

Compact small signal modeling and PSO-based input matching of a packaged CMOS LNA in subthreshold region

The paper reports a small-signal model of a cascaded, packaged, CMOS low noise amplifier (LNA) operating in subthreshold region. The proposed compact model has been verified through CADENCE simulations in standard 0.18 μm process. This model also accounts for the dominating role of some of the device parasitic capacitances in determining the input impedance of the amplifier. The closed form expression of the input impedance obtained-from this model is then used for synthesizing the input matching network of the common-source LNA using standard Q-based technique. It has been noted that the conventional Q-based matching approach does not provide symmetric matching characteristics (S₁₁) about the center frequency (900 MHz). To overcome this problem, a swarm intelligence-based evolutionary technique has been adopted for synthesis of the matching network. Symmetric nature is obtained both in terms of S₁₁ as well as the real/imaginary parts of the input impedance.     

Power analysis and design of wide dynamic range CMOS imaging sensors

Wide dynamic range (WDR) CMOS imaging sensors (CIS) are being designed for new portable, implantable and sensory applications, which demand low power consumption. Compared to normal CISs, high quality WDR CISs generally consume much more power. Up to now, the power consumption of a WDR CIS has never been formally studied. This paper focuses to model and analyze the power consumption of two major WDR CIS designs. Analytical equations are derived for the WDR CIS power, and are verified with HSPICE simulations. The analysis indicates that the power consumption of WDR CISs is dominated by the column bus driving power for large imaging array, while photocurrent related power is negligible. Hence, the WDR CIS power is heavily dependent on the load of the column bus and the read-out frequency. A new partial quantization scheme is developed to acquire WDR images with greatly reduced read-out frequencies. Its power consumption is also analytically derived and verified with HSPICE simulations. A 256×256 partial quantization column consumes about 124.0 nW/pixel in the CMOS process for 16-bit dynamic range and 30 Hz frame rate. The power analysis is further verified by experimental measurements of a proof-of-concept 32×32 partial quantization imaging sensor in the CMOS process.     

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

Computer aided analysis and design of MOS translinear circuits operating in strong inversion

Recently, it was proposed to generalize the well-known translinear circuit principle in such a way that it also applies to MOS transistors operated in strong inversion. In this paper, the MOS translinear (MTL) principle will be briefly reviewed. A graphical analysis method for MTL-circuits is presented, which can also be applied to bipolar translinear circuits. This graphical method was implemented in a computer program, which is now used as an interactive design tool to implement nonlinear signal processing functions by MTL circuits.     

Highly linear programmable balanced current scaling technique in moderate inversion

A technique to achieve highly linear current scaling in CMOS technologies is proposed. It is based on two balanced electronically programmable current mirrors operating in moderate inversion. The scaling factor can be continuously adjusted in a wide range. This technique can be employed to achieve or to extend gain adjustment in amplifiers. As an application example, a variable-gain differential current amplifier and a tunable transconductor are presented. Measurement results of the transconductor implemented in a 0.5-/spl mu/m CMOS technology validate in silicon the proposed approach.     

Highly linear and low noise differential bipolar MOSFET down-converter in CMOS process

A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 μm CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.     

A novel wide dynamic range silicon photodetector and linear imaging array

A novel silicon solid-state photodetector structure utilizing the MOSFET subthreshold effect was conceived, developed, fabricated, and experimental results were obtained. This photodetector device, which can be integrated on the same chip with MOSFET circuits or CCD's, provides an analog voltage signal over a wide dynamic range. Fabricated photodetector devices and arrays showed experimentally, in the visible spectrum, an incoming radiation detection light intensity dynamic range of greater than 10⁷. In addition, the novel photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. In this paper, we describe in detail the theory of the new photodetector device and its applications to form linear imaging arrays. Finally, we present experimental results obtained on developed and fabricated devices and arrays.     

A novel wide dynamic range silicon photodetector and linear imaging array

A silicon photodetector structure utilizing the MOSFET subthreshold effect is discussed. This photodetector, which can be integrated on the same chip with MOSFET circuits or CCDs, provides an analog voltage signal over a wide dynamic range. Photodetector and arrays showed, in the visible spectrum an incoming radiation-detection light-intensity dynamic range of greater than 10/SUP 7/. In addition, the photodetector device was used to realize CCD and self-scanned MOSFET linear arrays. The theory of the new photodetector device and its use in forming linear imaging arrays are discussed. Experimental results are presented.     

Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.     

一种新型的宽线性范围差分电压输入电流传输器及其应用

设计了一种带有共模检测电路的宽线性范围差分电压输入电流传输器(DVCCⅡ).所提出的电路具有动态的长尾电流的差分对,可获得较大的动态线性输入范围.所提出的电路可以得到精确跟随特性和宽线性输入范围,且比较已有电路具有低电压低功耗等特点.采用SMIC 0.18μm工艺,用Spectre对电路进行仿真,电源电压是1.8 V,...     

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However, the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators, the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition, design guidelines are suggested and test results are presented.     

基于90nmCMOS工艺的低功耗宽带压控振荡器设计

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 d Bc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185d Bc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.