A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O

A system chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and an SRAM-based embedded field-programmable gate array (FPGA). Application-specific bus-mapped coprocessors and flexible input/output peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customization. The silicon area required by the system is 20 mm/sup 2/ in a 0.18-/spl mu/m CMOS technology. The embedded FPGA accounts for about 40% of the system area.     

Circuit design of a novel FPGA chip FDP2008

A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.     

Modeling technology impact on cluster microprocessor performance

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.     

Programmable interconnects speed system verification

A family of CMOS integrated circuits called field programmable interconnect components (FPICs) that can provide designers with the high-density interconnect architectures for making programmable hardware a reality is discussed. The FPIC devices address a broad spectrum of interconnect needs, including system prototypes and breadboards, user-specific/configurable printed circuit boards (PCBs), application configurable processors, test interfaces, and programmable connector and switching matrix applications. Using FPIC devices for system prototyping, in conjunction with other programmable components (programmable logic devices (PLDs), field programmable gate arrays (FPGAs), microprocessors, microcontrollers, DSP, and programmable memory) enhance the design verification process, allowing faster, more flexible, and thorough product integration. Field programmable circuit boards (FPCBs) designed to take advantage of the high density interconnect and observability of FPIC devices and a FPIC/FPCB development environment are described     

软件无线电中AM调制解调算法的DSP实现

软件无线电的思想已推广到无线电通信领域,该技术依托于宽频段、特性均匀的天线,高速的AD/DA芯片,可编程大规模逻辑门阵列,通用高速的DSP数字信号处理芯片等硬件技术.介绍了AM调制和解调的数字化实现方法,给出了基于TMS320C32 DSP芯片实现AM调制解调算法的主要源程序.经测试,该软件设计在软件无线电硬件平台上运行良好,整个系统的各项性能指标均达到设计的要求.     

A New Field Programmable Gate Array: Architecture and Implementation

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below 20 Ω. The chip has been fabricated using a 0.8-μm n-well complementary metal oxide semiconductor technology with two layers of metalization.     

可编程PSoC的构成及其系统设计

将微控制器或DSP核、存储器、逻辑电路、I／O接口及其他功能模块综合在一颗芯片上，这样的系统解决方案，称之为片上系统SoC，SoC已经在各个领域得到了广泛的应用。由于处理器和存储器的可编程能力，使得这种以CPU为核心的解决方案具有很强的灵活性和可修改能力。在一个系统中．外设和I／O接口通常在设计时就琦定，相对的改变较小。相对于系统的其他部分而言，模拟电路部分的可编程能力是最小的。本文讨论的是Cypress公司的可编程片上系统PsoC的基本构成及其系统的设计。他在数字可编程的同时还具备有模拟电路的可编程能力。     

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle.     

A gallium arsenide SDFL gate array with on-chip RAM

Describes a GaAs gate array with on-chip RAM based on the Schottky diode field-effect transistor logic (SDFL) technology. The array features 432 programmable SDFL cells, 32 programmable interface input-output (I/O) buffers, and four 4/spl times/4 bit static random access memories (RAM) on a 147 mil/spl times/185 mil chip. Each SDFL cell can be programmed as a NOR gate with as many as 8 inputs with a buffered or unbuffered output or as a dual OR-NAND gate with four inputs per side. The interface I/O buffer can be programmed for ECL, TTL, CMOS, and SDFL logic families. Each 4/spl times/4 bit RAM is fully decoded using SDFL circuits (depletion-mode MESFET). Preliminary results demonstrate the feasibility of GaAs SDFL for fast gate array and memory applications.     

Co-Synthesis to a Hybrid RISC/FPGA Architecture

Hybrid architectures combining conventional processors with configurable logic resources enable efficient coordination of control with datapath computation. With integration of the two components on a single device, housekeeping tasks and, optionally, loop control and data-dependent branching, can be handled by the conventional processor, while regular datapath computation occurs on the configurable hardware. This paper describes a novel approach to programming such hybrid devices that gives the programmer control over mapping of data and computation between conventional processor and configurable logic. With a simple set of pragma and intrinsic function directives, the NAPA C language provides for manual control over perhaps the most important aspect of programming such hybrid devices. Alternatively, as experience is gained about tradeoffs between the two computational resources, mapping directives may eventually be generated by an external tool. The paper further describes a research prototype compiler that targets the hybrid processor model, with a concrete implementation for the National Semiconductor NAPA1000 chip. The NAPA C compiler parses the mapping directives, performs semantic analysis, and co-synthesizes a conventional processor executable combined with a configuration bit stream for the configurable logic. Two major compiler phases, the synthesis of pipelined loops and the datapath synthesis, are described in detail.     

AMULET2e: an asynchronous embedded controller

AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks     

Design and Implementation of Embedded Transmission Control Protocol/Internet Protocol Network Based on System-on-programmable Chip

A scheme of transmission control protocol/Internet protocol（TCP/IP） network system based on system-on-programmable chip（SOPC） is proposed for the embedded network communication. In this system, Nios processor, Ethernet controller and other peripheral logic circuits are all integrated on a Stratix Ⅱ field programmable gate array （FPGA） chip by using SOPC builder design software. And the network communication is realized by transplanting MicroC/OS Ⅱ （uC/OS Ⅱ ） operation system and light weight Internet protocol（LwIP）. The design idea, key points and the structures of both software and hardware of the system are presented and ran with a telecommunication example. The experiment shows that the embedded TCP/IP network system has high reliability and real-time performance.     

基于Zynq7020的组合导航处理平台软硬件系统的设计与实现

提出一种基于Zynq处理平台的组合导航系统设计及实现方案,Zynq7020作为新近发展的可扩展处理平台,集成了大规模可编程逻辑器件(FPGA)、低功耗高性能先进ARM处理器,两者通过内部总线互联与通信,满足高集成度、高性能数据处理的应用需求.基于Zynq处理器设计并实现组合导航处理平台,替代原有的FPGA+DSP+ARM导航解算模式,单芯片完成IMU信号采集,信号处理和导航解算等功能,降低整机设计的复杂度和成本.     

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.     

基于测试系统的FPGA逻辑资源的测试

FPGA在许多领域已经得到广泛应用,其测试问题也显得越来越突出。文章针对基于SRAM结构FPGA的特点,以Xilinx公司的XC4000系列芯片为例,利用检测可编程逻辑资源的多逻辑单元(CLB)混合故障的测试方法,阐述了如何在BC3192V50测试系统上实现FPGA的在线配置以及功能和参数测试。它是一种基于测试系统的通用的FPGA配置和测试方法。     

Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip     

The Architecture and Development Flow of the S5 Software Configurable Processor

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

EPON中基于NIOS的ONU设计

提出一种基于ALTERA公司的NIOS嵌入式微处理器的ONU(光网络单元)设计方案.通过将NIOS软核处理器、自定义逻辑模块、存储器和I/O集成到单块低成本的FPGA上,组成一个SOPC(片上可编程系统),实现以太网无源光网络中的ONU功能.与采用套片加软件来实现ONU的方案相比,该方案降低了系统的成本,复杂性和功耗.     

Design and simulation of novel TLG–SET based configurable logic cells

Single electron tunneling circuits seem to be promising candidates as basic circuit elements of the next generation ultra-dense VLSI and ULSI circuits for their ultra-low power consumption, ultra-small size, and rich functionality. In this paper, design and simulation of novel configurable logic cells (CLCs) using single electron tunneling (SET) technology based threshold logic gate (TLG) are presented. The proposed CLC can realize all Boolean logic functions by configuring the control bits without changing the structure of the circuit and the parameters of TLG–SET based design. The logic operation of the circuit is simulated using Monte Carlo simulation. According to the simulation results, the circuit operation based on the transfer of single electrons between adjacent islands is stable.     

A survey of FPGA design for AI era

FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of DNN.For ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC operation.The other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of DNN.For memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/5.Other designs are new architecture and specialized AI engine.Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform.Its AI engine can provide up to 8X silicon compute density.Intel AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.