Low-component-count active-only immittance and their application inrealising simple multifunction biquads

The authors present a class of second-order immittance simulation circuits and derive an exemplary multifunction voltage mode biquad. These circuits are realisable with only internally compensated type operational amplifiers and OTAs and do not require any external resistors or capacitors. Because of their active-only nature, the circuits are suitable for implementation in both bipolar or CMOS technologies. The workability of the circuits has been demonstrated by experimental results based upon a μA741 type IC operational amplifier and a CA 3080 type IC OTA     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters

Recent progress of wide-band communication systems demands high-frequency circuits. Conventionally, the linearity of the operational transconductance amplifier and capacitor (OTA-C) has been analyzed using Taylor series expansion. Unfortunately, this approach does not predict the frequency-dependent linearity degradation. Thus, to properly design linearized OTAs, the frequency dependence of these coefficients must be determined. In this paper, we present a frequency-dependent harmonic-distortion analytical method applied to a linear-enhanced OTA. This OTA, which is suitable for high-frequency operation, uses three linearization techniques simultaneously: 1) attenuation through floating-gate MOS transistors; 2) source degeneration; and 3) polynomial cancellation techniques. By using the harmonic-distortion analysis, some properties on the performance of OTA are used to improve the performance of OTA-C based circuits at high frequencies. A 0.5-/spl mu/m CMOS OTA simulation and experimental results are shown to verify the harmonic-distortion analytical method.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

A 0.5 V bulk-input OTA with improved common-mode feedback for low-frequency filtering applications

This paper presents the design of a two-stage pseudo-differential operational transconductance amplifier (OTA) and its application in low-frequency continuous time filters. The OTA was designed in a 0.18 μm, 0.45 V V _T CMOS process. An improved bulk-mode common-mode feedback (CMFB) circuit has been designed which does not load the OTA compared to prior art. A self cascode load structure and partial positive feedback provide higher gain. The bulk terminals of all transistors have been biased to lower their threshold voltages (V_T) and maximize signal swing. The OTA operates at a supply voltage of 0.5 V and consumes only 28 μW of power. Rail-to-rail input is made possible by using the transistor’s bulk terminal as the input. For a load of 20 pF the OTA has a measured DC gain of 63 dB and a gain-bandwidth product of 570 kHz. To demonstrate the use of the OTA in practical circuits, three active RC filters were designed: a 10 kHz Butterworth filter, a 10 kHz Bessel filter, and a 2.5 kHz Tschebycheff filter.     

Transconductance amplifier structures with very smalltransconductances: a comparative design approach

A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small G_m's (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-μm n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results     

New grounded passive elements-based external multiplier-less memelement emulator to realize the floating meminductor and memristor

A novel memelement emulator configuration has been reported in the presented work. This proposed configuration can be used to realize the function of a floating meminductor as well as the memristor element through proper selection of employed passive elements. The presented emulator circuit is based on MVDCC (modified VDCC) and OTA, which are CMOS implemented electronically tunable ABBs (Active Building Blocks). The designed circuit employs only two ABBs and three grounded passive elements. As per the knowledge of the authors, no such emulation configuration with a floating architecture has been reported so far, which can realize the behaviour of two mem-elements without the use of any external multiplier IC/circuitry, passive inductor or mutation through any externally employed memelement. It can be considered as a notable design feature along with its other advantages like electronically/resistively tunable emulated response and use of only grounded passive elements. Moreover, proposed circuit has been investigated for the consideration of non-idealities and different port parasitics of employed blocks. For the verification purpose, PSPICE simulation environment with CMOS 0.18 µm TSMC technology parameters, has been selected. The functioning of the realized meminductive and memristive behaviour has also been verified through the application example circuits designed using developed emulator circuit. Afterwards, the commercial IC based realization of the proposed emulator circuit has been shown and experimental results are discussed.

     

基于控阈技术的电流型CMOS全加器的通用设计方法

利用电流信号的阈值易于控制这一特点,对电流型CMOS电路中如何实现阈值控制进行了研究.以开关信号理论为指导,建立了实现阈值控制电路的电流传输开关运算并具体指导设计了具有阈值控制功能的二值和多值电流型CMOS全加器.提出了适用于任意逻辑值的可控阈电流型CMOS全加器的通用设计方法.通过对开关单元实施阈值控制后,所设计的电路在结构上得到了非常明显的简化,在性能上也获得了改善.最后给出了采用0.25μm CMOS工艺参数的HSPICE模拟结果及其能耗比较.     

Synthesis of programmable multi-input current-mode linear analog circuits

This paper reports synthesis methodologies for linear analog circuits. A generalized multi-input operational transconductance amplifier (OTA) network has been synthesized that can be easily programmed to realize different analog functions. The design of the multifunction network has been realized without any switches. The inherent characteristic of OTA as a voltage-to-current (V-I) converter with differential input has been exploited in the synthesis procedure. Efficient analog circuits synthesized with programmable OTA network are reported along with simulation results. The theoretical analysis supported by extensive experimental results confirms low sensitivity, high-frequency response, and efficient programmability of the proposed OTA network to realize different types of filters.     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit     

基于跨导放大器的电流模式积分单元的设计

在集成电路系统中,各种模拟功能的电流单元都是由基本的电流模单元组成。跨导放大器是电流模电路的基本单元。基于跨导放大器的电流模积分器可以实现电流到电流的积分转换。同时可应用于各种集成滤波电路的设计。在此采用0．18ptmCMOS仿真工艺,使用共源共栅结构设计一款供电电压为1．8V的高增益低功耗的跨导放大器,采用具有PTAT基准电流源的偏置电路,使用HSpice进行优化设计,并将此放大器应用于电流模式积分单元的电路仿真。     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

CMOS fully differential second-generation current conveyor

The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 μm CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented     

An all-implanted CCD/CMOS process

A process has been developed that combines double-polysilicon, surface-type, n-channel charge-coupled devices (CCD's) with silicon-gate CMOS circuits on the same substrate. The process is all ion-implanted (including the getter step), requires only one more masking step than the 18-V CMOS flow, and is fully compatible with the 5-µm-gate-length silicon-gate Planox (localized oxidation of silicon) CMOS process. To demonstrate the design flexibility afforded by the availability of both p- and n-channel transistors, CCD shift registers with CMOS peripheral circuits and a silicon-gate CMOS operational amplifier have been designed and characterized. Low-pass and band-pass filters have also been designed and characterized and found to be comparable with those fabricated through the conventional CCD/NMOS process.     

Design and application of pipelined dynamic CMOS ternary logic andsimple ternary differential logic

Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2-μm CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown     

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1$,times,$ VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.      

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

A highly linear bulk-driven CMOS OTA for continuous-time filters

In this paper we present a bulk-driven CMOS triode-based fully balanced operational transconductance amplifier (OTA) and its application to continuous-time filters. The proposed OTA is linearly tunable with the feature of low distortion and high output impedance. It can achieve wide input range without compromising large transconductance tuning interval. Using a 0.18 μm n-well CMOS process, we have implemented a third-order elliptic low-pass filter based on the proposed OTA. Both the simulation and measurement results are reported. The total harmonic distortion is more than −45 dB for fully differential input signals of up to 0.8 V peak–peak voltage. A dynamic range of 45 dB is obtained under the OTA noise integrated over 1 MHz.     

Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current     

7-decade tuning range CMOS OTA-C sinusoidal VCO

A new operational transconductance amplifier-capacitor (OTA-C) based sinusoidal voltage-controlled oscillator (VCO) has been designed and fabricated. The oscillation frequency of which can be tuned from 74 mHz to 1 MHz. The VCO uses a new OTA whose transconductance is adjusted by using a set of special current mirrors. These current mirrors operate in weak inversion and their gain can be controlled continuously through a gate voltage over many decades. This is the first report of such a wide tuning range for CMOS sinusoidal oscillators. Experimental results are provided