A Simplified Decoding Algorithm Using Symbol Transformation for Turbo Pragmatic Trellis‐Coded Modulation

This paper presents the application of a turbo coding technique combined with a bandwidth efficient method known as trellis‐coded modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf binary/quadrature phase shift keying (B/QPSK) turbo decoder without any modifications. A conventional turbo decoder then operates on transformed symbols to estimate the coded bits. The uncoded bits are decoded based on the estimated coded bits and locations of the received symbols.     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

Carrier phase recovery for turbo‐coded systems with pre‐coded GMSK modulation

A carrier phase recovery scheme suited for turbo‐coded systems with pre‐coded Gaussian minimum shift keying (GMSK) modulation is proposed and evaluated in terms of bit‐error‐rate (BER) performance. This scheme involves utilizing the extrinsic information obtained from the turbo‐decoder to aid an iterative carrier phase estimation process, based on a maximum‐likelihood (ML) strategy. The phase estimator works jointly with the turbo‐decoder, using the updated extrinsic information from the turbo‐decoder in every iterative decoding. A pre‐coder is used to remove the inherent differential encoding of the GMSK modulation. Two bandwidths of GMSK signals are considered: BT=0.5 and 0.25, which are recommended by the European Cooperation for Space Standardization (ECSS). It is shown that the performance of this technique is quite close to the perfect synchronized system within a wide range of phase errors. This technique is further developed to recover nearly any phase error in [?π,+π] by increasing the number of phase estimators and joint decoding units. This, however, will increase the complexity of the system. Copyright © 2008 John Wiley & Sons, Ltd.     

Semi-Iterative Analog Turbo Decoding

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm² in a 0.25-mum BiCMOS process.     

A low power turbo/Viterbi decoder for 3GPP2 applications

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.     

Performance of multilevel‐turbo codes with blind/non‐blind equalization over WSSUS multipath channels

In this paper, in order to improve error performance, we introduce a new type of turbo codes, called ‘multilevel‐turbo codes (ML‐TC)’ and we evaluate their performance over wide‐sense stationary uncorrelated scattering (WSSUS) multipath channels. The basic idea of ML‐TC scheme is to partition a signal set into several levels and to encode each level separately by a proper component of the turbo encoder. In the considered structure, the parallel input data sequences are encoded by our multilevel scheme and mapped to any modulation type such as MPSK, MQAM, etc. Since WSSUS channels are very severe fading environments, it is needed to pass the received noisy signals through non‐blind or blind equalizers before turbo decoders. In ML‐TC schemes, noisy WSSUS corrupted signal sequence is first processed in equalizer block, then fed into the first level of turbo decoder and the first sequence is estimated from this first Turbo decoder. Subsequently, the other following input sequences of the frame are computed by using the estimated input bit streams of previous levels. Here, as a ML‐TC example, 4PSK 2 level‐turbo codes (2L‐TC) is chosen and its error performance is evaluated in WSSUS channel modelled by COST 207 (Cooperation in the field of Science & Technology, Project #207). It is shown that 2L‐TC signals with equalizer blocks exhibit considerable performance gains even at lower SNR values compared to 8PSK‐turbo trellis coded modulation (TTCM). The simulation results of the proposed scheme have up to 5.5 dB coding gain compared to 8PSK‐TTCM for all cases. It is interesting that after a constant SNR value, 2L‐TC with blind equalizer has better error performance than non‐blind filtered schemes. We conclude that our proposed scheme has promising results compared to classical schemes for all SNR values in WSSUS channels. Copyright © 2005 John Wiley & Sons, Ltd.     

A low‐complexity MSK‐based M‐ary cyclic‐shift keying transceiver for direct sequence spread spectrum system over multipath fading channels

In this paper, a low‐complexity spread spectrum system with M‐ary cyclic‐shift keying (MCSK) symbol spreading is proposed. In addition, by using the minimum‐shift‐keying (MSK) as the chip‐level modulation, we obtain a high‐rate QPSK‐MCSK transceiver scheme which not only provides a constant‐envelop and continuous‐phase transmitted signal, but can also achieve a better performance than the conventional direct sequence spread spectrum (DSSS) system. At the transmitter, the data stream is first mapped into QPSK‐MCSK symbols in terms of orthogonal Gold code sequences, then followed by the cyclic prefix (CP) insertion for combating the interblock interference, and finally applying the MSK scheme to maintain the constant‐envelope property. The receiver first performs MSK demodulation, then CP removal, and finally the channel‐included MCSK despreading and symbol demapping. Furthermore, the single input single output (SISO) QPSK‐MCSK transceiver can be easily extended to the multiple input single output (MISO) case by incorporating the space–time block coding for high‐link quality. Simulation results show that the proposed SISO and MISO QPSK‐MCSK systems significantly outperform the conventional DSSS counterparts under the AWGN channel, and attain a more robust performance under the multipath fading channel. Copyright © 2011 John Wiley & Sons, Ltd.     

A simple soft linear detection for coded multi‐input multi‐output systems

We propose a very simple and efficient soft linear multi‐input multi‐output (MIMO) detection scheme. The detection process is divided into two separate problems. The proposed scheme first detects MIMO symbols using conventional linear detection methods and produces soft bit information using a simple soft demapping method. Next, we refine the soft information by accounting for uneven post‐detection noise variance across MIMO layers. From the simulation result investigated in this paper, we first emphasize that powerful channel coding may suppress the differences of diversity gains among various MIMO detection schemes. This implies that the channel decoding operation may not be transparent to performance gain that resulted from MIMO detection process. The proposed scheme concentrates on accurate estimation of soft post‐MIMO detected information in a very simple manner, rather than concentrating on a complex MIMO detection scheme prior to decoding process. In combination with turbo codes, the proposed scheme produces comparable performance to maximum likelihood detection, even with the simplest scheme such as zero forcing detection, with drastically reduced complexity. Copyright © 2011 John Wiley & Sons, Ltd.     

Design of AT‐DMB Baseband Receiver SoC

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT‐DMB) baseband receiver SoC. The AT‐DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T‐DMB system; therefore, a conventional T‐DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT‐DMB baseband receiver SoC is fabricated using 0.13 µm technology and shows successful operation with a 50 mW power dissipation.     

New stopping criteria for iterative decoding of LDPC codes in H‐ARQ systems

Under severely unreliable channel, decoding of error‐correcting codes frequently fails, which requires a lot of computational complexity, especially, in the iterative decoding algorithm. In hybrid automatic repeat request systems, most of computation power is wasted on failed decoding if a codeword is retransmitted many times. Therefore, early stopping of iterative decoding needs to be adopted. In this paper, we propose a new stopping algorithm of iterative belief propagation decoding for low‐density parity‐check codes, which is effective on both high and low signal‐to‐noise ratio ranges and scalable to variable code rate and length. The proposed stopping algorithm combines several good stopping criteria. Each criterion is extremely simple and will not be a burden to the overall system. With the proposed stopping algorithm, it is shown via numerical analysis that the decoding complexity of hybrid automatic repeat request system with adaptive modulation and coding scheme can be fairly reduced. Copyright © 2012 John Wiley & Sons, Ltd.     

EM‐based iterative receiver for coded MIMO systems in unknown spatially correlated noise

We present iterative channel estimation and decoding schemes for multi‐input multi‐output (MIMO) Rayleigh block fading channels in spatially correlated noise. An expectation‐maximization (EM) algorithm is utilized to find the maximum likelihood (ML) estimates of the channel and spatial noise covariance matrices, and to compute soft information of coded symbols which is sent to an error‐control decoder. The extrinsic information produced by the decoder is then used to refine channel estimation. Several iterations are performed between the above channel estimation and decoding steps. We derive modified Cramer–Rao Bound (MCRB) for the unknown channel and noise parameters, and show that the proposed EM‐based channel estimation scheme achieves the MCRB at medium and high SNRs. For a bit error rate of 10⁻⁶ and long frame length, there is negligible performance difference between the proposed scheme and the ideal coherent detector that utilizes the true channel and noise covariance matrices. Copyright © 2006 John Wiley & Sons, Ltd.     

Assembled space-time turbo trellis codes

A novel full rate space-time turbo trellis code, referred to as an assembled space-time turbo trellis code (ASTTTC), is presented in this paper. For this scheme, input information binary sequences are first encoded using two parallel concatenated convolutional encoders. The encoder outputs are split into four parallel streams and each of them is modulated by a QPSK modulator. The modulated symbols are assembled by a predefined linear function rather than punctured as in the standard schemes. This results in a lower code rate and a higher coding gain over time-varying fading channels. An extended two-dimensional (2-D) log-MAP (maximum a posteriori probability) decoding algorithm, which simultaneously calculates two a posteriori probabilities (APP), is developed to decode the proposed scheme. Simulation results show that, under the same conditions, the proposed code considerably outperforms the conventional space-time turbo codes over time-varying fading channels.     

一种短延时Turbo编码调制系统的设计

本文设计了一种比传统体制减少了一半延时的Turbo编码调制系统,介绍了交织器的相关限制.提出了一种在译码过程中对信道值的估计方法,使得外信息的计算更加趋于精确,从而提高了译码性能.这种迭代译码算法是标准格码调制译码算法的一种自然推广,同时也类似于二元Turbo码在BPSK调制下的逐比特译码算法.采用吞吐率为2bits/s/Hz的8PSK调制,比特错误率为10^-5所需的信噪比与Shannon限相距不到0.4dB.     

Bandwidth-efficient turbo trellis-coded modulation using puncturedcomponent codes

We present a bandwidth-efficient channel coding scheme that has an overall structure similar to binary turbo codes, but employs trellis-coded modulation (TCM) codes (including multidimensional codes) as component codes. The combination of turbo codes with powerful bandwidth-efficient component codes leads to a straightforward encoder structure, and allows iterative decoding in analogy to the binary turbo decoder. However, certain special conditions may need to be met at the encoder, and the iterative decoder needs to be adapted to the decoding of the component TCM codes. The scheme has been investigated for 8-PSK, 16-QAM, and 64-QAM modulation schemes with varying overall bandwidth efficiencies. A simple code choice based on the minimal distance of the punctured component code has also been performed. The interset distances of the partitioning tree can be used to fix the number of coded and uncoded bits. We derive the symbol-by-symbol MAP component decoder operating in the log domain, and apply methods of reducing decoder complexity. Simulation results are presented and compare the scheme with traditional TCM as well as turbo codes with Gray mapping. The results show that the novel scheme is very powerful, yet of modest complexity since simple component codes are used     

Low-power log-MAP decoding based on reduced metric memory access

Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards such as W-CDMA and CDMA2000. Although several low-power techniques have been proposed, power consumption is still a major issue to be solved in practical implementations. Since turbo decoding is classified as a memory-intensive algorithm, reducing memory accesses is crucial to achieve a low power design. To reduce the number of memory accesses for maximum a posteriori (MAP) decoding, this paper proposes an approximate reverse calculation method that can be implemented with simple arithmetic operations such as addition and comparison. Simulation results show that the proposed method applied to the W-CDMA standard reduces the access rate of the backward metric memory by 87% without degrading error-correcting performance. A prototype log-MAP decoder based on the proposed reverse calculation achieves 29% power reduction compared to a conventional decoder that does not use the reverse calculation.     

Refined channel estimation for coherent detection of turbo codesover flat-fading channels

Channel state information is required for the coherent detection and decoding of turbo codes transmitted over flat-fading channels. A channel estimation technique suitable for turbo codes is presented. The technique uses pilot symbols to obtain initial channel estimates, and refines the estimates after each iteration of the turbo decoder     

Iterative decoding of codes over complex numbers for impulsive noise channels

We discuss the decoding of error-correcting block codes over complex numbers for the transmission over impulsive noise channels. The encoder multiplies a vector of complex information symbols resulting from a modulation scheme, e.g., quadrature amplitude modulation (QAM), with a unitary generator matrix G. Choosing the inverse Fourier transform as G, the encoding procedure is similar to orthogonal frequency-division multiplex (OFDM) modulation. The maximum a posteriori (MAP) receiver is analyzed and a suboptimum decoder based on the turbo decoding principle is derived. Simulation results show the excellent performance of the iterative decoder.     

On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes

In this paper, both performance and complexity aspects of two-dimensional single parity check turbo product codes (I-SPC-TPC) are investigated. Based on the proposed I-SPC-TPC coding scheme, a parallel decoding structure is developed to increase the decoding throughput with minor performance degradation compared with the serial structure. For both decoding architectures, a new helical interleaver is constructed to further improve the coding gain. In terms of decoding algorithm, the extremely simple Sign-Min decoding is alternatively derived with only three additions needed to compute each bit's extrinsic information. For performance evaluation, (16, 14, 2)² single parity check turbo product code with code rate 0.766 over AWGN channel using QPSK modulation is considered. The simulation results using Sign-Min decoding show that it can achieve bit-error-rate of 10^?5 at signal-to-noise ratio of 3.8 dB with 8 iterations. Compared to the same rate and codeword length turbo product code composed of extended Hamming codes, the considered scheme can achieve similar performance with much less complexity. Important implementation issues such as the finite precision analysis, efficient sorting circuit design and interleaver memory management are also presented.     

Design and performance of BICM-ID systems with hypercube constellations

This paper introduces new mappings of QPSK symbols, viewed as a multi-dimensional hypercube, to improve the performance of bit-interleaved coded modulation with iterative decoding (BICM-ID). By evaluating the upper bound of the bit error rate performance of BICM-ID, a condition to find the best mapping of a hypercube constellation in terms of the asymptotic performance under different channel models is established. A general and simple algorithm to construct the best mapping of a hypercube is then proposed. Analytical and simulation results show that the use of the proposed mappings together with very simple convolutional codes can offer significant coding gains over the conventional BICM-ID systems for all the channel models considered. Such coding gains are achieved without bandwidth or power expansion and with a very small increase in the system complexity.     

Network‐coded MIMO‐NOMA systems with FEC codes in two‐way relay networks

This paper assumes two users and a two‐way relay network with the combination of 2×2 multi‐input multi‐output (MIMO) and nonorthogonal multiple access (NOMA). To achieve network reliability without sacrificing network throughput, network‐coded MIMO‐NOMA schemes with convolutional, Reed‐Solomon (RS), and turbo codes are applied. Messages from two users at the relay node are network‐coded and combined in NOMA scheme. Interleaved differential encoding with redundancy (R‐RIDE) scheme is proposed together with MIMO‐NOMA system. Quadrature phase‐shift keying (QPSK) modulation technique is used. Bit error rate (BER) versus signal‐to‐noise ratio (SNR) (dB) and average mutual information (AMI) (bps/Hz) versus SNR (dB) in NOMA and MIMO‐NOMA schemes are evaluated and presented. From the simulated results, the combination of MIMO‐NOMA system with the proposed R‐RIDE‐Turbo network‐coded scheme in two‐way relay networks has better BER and higher AMI performance than conventional coded NOMA system. Furthermore, R‐RIDE‐Turbo scheme in MIMO‐NOMA system outperforms the other coded schemes in both MIMO‐NOMA and NOMA systems.