12位100 MS/s流水线A/D转换器的参考电压缓冲器

分析了参考电压精度对流水线A/D转换器性能的影响,并通过Matlab建模仿真,得到了12位流水线A/D转换器对参考电压精度的要求,即参考电压精度要达到10位以上.提出了一种新型的参考电压缓冲器结构,通过增加两个静态比较器,有效地提高了缓冲器的精度.采用SMIC 0.35 μm 3.3 V CMOS工艺,为一个12位100 MHz采样频率的流水线A/D转换器设计了电压值为1.65 V±0.5 V的参考电压输出缓冲器.Hspice后仿真结果显示,各个工艺角下,缓冲器可将干扰对1 V的差分输出的影响控制在0.35 mV以内.该缓冲器可以达到10位以上精度,能够满足12位100 MS/s流水线A/D转换器的设计要求.     

基准电压波动对Σ-Δ A/D转换性能的影响

Σ-ΔA/D转换器需要一个基准电压作为参照进行模/数转换,因此,基准电压上的任何变化都会直接影响到A/D转换的结果。文章推导分析了基准电压的DC及AC波动对Σ-ΔA/D转换结果的影响机制,并用一个三阶Σ-ΔA/D转换器实例,在Matlab仿真环境中验证了分析结果。文章的结论可用于指导Σ-ΔA/D转换器芯片中带隙基准源模块的电源抑制比设计。     

A/D转换器参考电压的软件校正

为了消除参考电压波动对A/D转换结果的影响,研究了参考电压波动和温度效应对A/D转换器转换精度的影响机理及其校正方法。利用实验数据得到了参考电压变化和温度效应与转换精度的关系,结合误差理论,分析得出了基于复合校正系数的软件校正算法。实践证明:该算法补偿效果良好,可保证A/D转换的精度。     

并行分时流水线A/D转换器系统级研究

基于并行分时A/D转换器的理论研究,对该类型A/D转换器进行了系统行为级设计和仿真。分析了系统中并行误差及流水线A/D转换器等误差源对整个系统性能的影响。通过计算机仿真,给出了系统模块的设计参数。通过理论分析与系统仿真,为并行分时流水线A/D转换器的设计提供了理论依据和数据参考,为该类型A/D转换器提供了设计优化方向。     

0.18 μm 1.8 V 10 bit 100 MS/s CMOS电流舵D/A IP设计与验证

基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器.当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB.在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求.     

一种用于高速14位A/D转换器的采样/保持电路

介绍了一种采用0.35 μm CMOS工艺的开关电容结构采样/保持电路.电路采用差分单位增益结构,通过时序控制,降低了沟道注入电荷的影响;采用折叠共源共栅增益增强结构放大器,获得了要求的增益和带宽.经过电路模拟仿真,采样/保持电路在80 MSPS、输入信号(Vpp)为2 V、电源电压3 V时,最大谐波失真为-90 dB.该电路应用于一款80 MSPS 14位流水线结构A/D转换器.测试结果显示:A/D转换器的DNL为0.8/-0.9 LSB,INL为3.1/-3.7 LSB,SNR为70.2 dB,SFDR为89.3 dB.     

基准电压波动对∑-△A／D转换性能的影响

∑-△A／D转换器需要一个基准电压作为参照进行模／数转换，因此，基准电压上的任何变化都会直接影响到A／D转换的结果。文章推导分析了基准电压的DC及AC波动对∑-△A／D转换结果的影响机制，并用一个三阶∑-△A／D转换器实例，在Matlab仿真环境中验证了分析结果。文章的结论可用于指导∑-△A／D转换器芯片中带隙基准源模块的电源抑制比设计。     

JSM—T_(300)扫描电镜物镜电路分析

扫描电镜的物焦镜距与加速电压和物镜电流有关。扫描电镜要求物镜电流具有较大的变化范围。T_300扫描电镜物镜电路如图所示。IC8为D/A转换器。波段开关S_3、二极管矩阵电路(D_10～D_27)、R_52～R_60、R_B_(23)组成了二进制码编码电路,为D/A转换器提供八位二进制码。D_8、R_(50)、IC9_1组成的电路为D/A转换器提供参考模拟电压V_REF。D_8(IS2192)的稳压值为8.2V,即A点的电压为8.2V。电压跟随器IC9_1输出的电压V_B=V_REF=V_A=8.2V。D/A转换器的输出电压Vout=-(V_REF/R_49)·R_51(A_8/2~1+A_7/2~2+A_6/2~3+A_5/2~4+A_4/2~5+A_3/2~6+A_2/2~7+A_1/2~8)。若当S_3的刀与第一掷相接时,D_10导通,D_11～D_27均不导通,D/A转换器的数字输入端A_8=0,A_7～A_1,均为1。因此D/A转换器的输出电压Vout=4V。D/A转换器的输入状态和输出电压与S_3对应关系如表1所示。从中可看到D/A转换器的输出电压范围为-4～-8.1V。D/A转换     

一种单环5阶高精度音频Δ-Σ A/D转换器

采用英飞凌0.11μm CMOS工艺,实现了一种用于音频范围的高精度Δ-ΣA/D转换器。调制器采用1位量化的5阶单环前馈结构,ADC过采样率为256。A/D转换器模拟调制器工作于5V电压,数字滤波器工作于1.2V电压,整体功耗为20.52mW,版图面积3.1mm2。仿真结果显示,设计的A/D转换器在20kHz信号带宽内达到108.9dB的信噪失真比,有效位数为18位。     

一种单环5阶高精度音频△-∑ A/D转换器

采用英飞凌0.11 μm CMOS工艺,实现了一种用于音频范围的高精度△-∑ A/D转换器.调制器采用1位量化的5阶单环前馈结构,ADC过采样率为256.A/D转换器模拟调制器工作于5V电压,数字滤波器工作于1.2V电压,整体功耗为20.52 mW,版图面积3.1 mm2.仿真结果显示,设计的A/D转换器在20 kHz信号带宽内达到108.9 dB的信噪失真比,有效位数为18位.     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.     

一种新的多值A/D转换器

通过对三值 A/ D转换数学表示的分析 ,设计了二种三值 A/ D转换器电路。该转换器电路具有结构简单、低功耗、小型化和高信息密度等优点 ,它可进一步完善多值数字系统的研究     

单缸汽油发动机电控系统设计

针对传统发动机使用的化油器反应滞后、控制不精确、排放污染大的问题,以某款单缸化油器式汽油发动机为研究对象,设计了基于MC9S12XS128单片机的电子控制系统。文中分析了单片机对A/D转化信号的采集要求,设计了各个传感器的信号处理电路及驱动电路。通过对发动机工作过程的分析,对整个控制程序进行了模块化设计,并对主要模块的控制算法进行了阐述。实验结果表明,该系统使得发动机的动力性得到了提高,最大功率约提高了6.62%,同时提高了经济性,燃油消耗量（每小时油耗）降低了5.26%,验证了电控系统的有效性。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.