Intermediacy Prediction for High Speed Berger Code Checkers

We present an intermediacy prediction method that can be used to designhigh speed checkers for Berger codes, as well as for any other unordered code. In the proposed method, the received information and check bits are processed simultaneously toward an intermediate result. A two-rail code checker is then used to compare the two versions of such an intermediate result. Recall that, in conventional checkers for unordered codes, the received check bits remain idle until the received information bits are converted to the re-generated check bits. Therefore, our proposed intermediacy prediction method allows a checker's speed improvement. We show the application of our method to two well-Bergercode checker architectural solutions: (1) the threshold function based implementation, and (2) the Berger code partitioning design. We have verified that, as expected, the proposed method can improve the detecting speed of these existing solutions with moderate or minimum increase, and sometimes decrease, in hardware complexity.     

Design of Embedded Self-Testing Checkers for t-UED and BUED Codes

In this article we present a new method for designing self-testing checkers for t-UED and BUED codes. The main idea of this method is to map words of the considered code to words of a code of the same type in which the value of t or the number of check bits is reduced and repeating this with the obtained words until a parity code is obtained, or to translate the code words into words of a code for which such a mapping is possible. First we consider Borden codes for t = 2 ^k – 1, Bose, and Bose-Lin codes. The mapping operation is realized by averaging weights and check symbol values of the code words. The resulting checkers have a simple and regular structure. This structure is independent on the set of code words that is provided by the circuit under check. The checkers are very well suited for use as embedded checkers since they are self-testing with respect to single stuck-at faults under very weak assumptions. All three checker types can be tested with 2 or 3 code words. We also propose a novel approach to design checkers for Blaum codes that require much less code word tests than existing solutions.     

Design of some new efficient balanced codes

A balanced code with r check bits and k information bits is a binary code of length k+r and cardinality 2^k such that each codeword is balanced; that is, it has [(k+r)/2] 1's and [(k+r)/2] 0's. This paper contains new methods to construct efficient balanced codes. To design a balanced code, an information word with a low number of 1's or 0's is compressed and then balanced using the saved space. On the other hand, an information word having almost the same number of 1's and 0's is encoded using the single maps defined by Knuth's (1986) complementation method. Three different constructions are presented. Balanced codes with r check bits and k information bits with k⩽2^r+1-2, k⩽3×2^r-8, and k⩽5×2^r-10r+c(r), c(r)∈{-15, -10, -5, 0, +5}, are given, improving the constructions found in the literature. In some cases, the first two constructions have a parallel coding scheme     

On balanced codes

In a balanced code each codeword contains equally many 1's and 0's. Parallel decoding balanced codes with 2^r (or 2^r -1) information bits are presented, where r is the number of check bits. The 2²-r-1 construction given by D.E. Knuth (ibid., vol.32, no.1, p.51-3, 1986) is improved. The new codes are shown to be optimal when Knuth's complementation method is used     

校园安防智能电话报警系统设计与实现

基于现有公共电话网络,结合射频无线通信及传感器技术,设计开发一种用于校园安防的智能报警系统。系统在探测器端上加入编码发射电路,每个探测器编码由12位组成,编码信号包括探测器的位置信息和探测器类别信息。报警终端采用无线接收方式接收编码信号,用单片机软件译码取代专用集成电路芯片硬件译码,12位编码数据位中的位置信息编码位数和探测器种类编码位数可根据实际使用场合灵活定义,突破了采用集成芯片译码只有4～6位数据位的局限性。实验结果表明:探测器无线发送距离为200 m,在8位位置信息码,4位探测器种类信息码,每位两种状态的编码方式下,每个报警终端可接入探测器的数量达256个。     

通用CRC校验码编码计算程序

在简单地讨论了循环码基本特性的基础上,导出了一个利用程序计算循环系统码的校验位的流程。按照导出的流程用QBASIC语言编制了一个通用的CRC校验码编码的计算程序。利用给出的程序,可方便地计算出任意给定的码生成多项式及信息码元下对应的系统码的CRC校验位。     

Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes

Code checkers that monitor the outputs of a system can detect both permanent and transient faults. We present two novel architectures of embedded self-testing checkers for low-cost and cyclic arithmetic codes, one based on code word generators and adders, the other based on code word accumulators. In these schemes, the code checker receives all possible code words but one, irrespective of the number of different code words that are produced by the circuit under check (CUC). So any code checker can be employed that is self-testing for all or a particular subset of code words, and the structure of the code checker need not be tailored to the set of code words produced by the CUC. The proposed code word generators and accumulators are built from simple standard hardware structures, counters and end-around-carry adders. They can also be utilized in an off-line BIST environment as pattern generators and test response compactors.     

岸船卫星双向对时应用系统IRIG-B码设计

介绍了现行标准时间码IRIG-B码的编码方式,为满足岸船对时应用系统设计要求,提高岸船时间比对精度,对现行标准时间码IRIG-B码信息格式约定进行了重新设计,使新的IRIG-B码不仅携带时间信息,同时携带测量误差信息、位置信息、控制信息,并在信息位中加入检验位。考虑卫星信道的误码特性,利用空余码位进行纠错编码。仿真结果表明,在不增加卫星传输带宽的前提下,BCH编码可提高传输可靠性。     

Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes

This paper presents a procedure for synthesizing sequential machines with concurrent error detection based on Bose-Lin codes. Bose-Lin codes are an efficient solution for providing concurrent error detection as they are separable codes and have a fixed number of check bits, independent of the number of information bits. Furthermore, Bose-Lin code checkers have a simple structure as they are based on modulo operations. Procedures are described for synthesizing circuits in a way that their structure ensures that all single-point faults can only cause errors that are detected by a Bose-Lin code. This paper presents an efficient scheme for concurrent error detection in sequential circuits with no constraint on the state encoding. Concurrent error detection for both the state bits and the output bits is based on a Bose-Lin code and their checking is combined such that one checker suffices. Results indicate low area overhead. The cost of concurrent error detection is reduced significantly compared to other methods based on other codes.     

一种专用可重配置的FPGA嵌入式存储器模块的设计和实现

本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write_first、no_change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想.     

Lowering power consumption in concurrent checkers via input ordering

This paper presents an efficient and scalable technique for lowering power consumption in checkers used for concurrent error detection. The basic idea is to exploit the functional symmetry of concurrent checkers with respect to their inputs, and to order the inputs such that switching activity (and hence power consumption) in the checker is minimized. The inputs of the checker are usually driven by the outputs of the function logic and check symbol generator logic-spatial correlations between these outputs are analyzed to compute an input order that minimizes power consumption. The reduction in power consumption comes at no additional impact to area or performance and does not require any alteration to the design flow. It is shown that the number of possible input orders increases exponentially in the number of inputs to the checker. As a result, the computational cost of determining the optimum input order can be very expensive as the number of inputs to the checker increases. This paper presents a very effective technique to build a reduced cost function to solve the optimization problem to find a near optimal input order. It scales well with increasing number of inputs to the checker, and the computational costs are independent of the complexity of the checker. Experimental results demonstrate that a reduction in power consumption of 16% on the average for several types of checkers can be obtained using the proposed technique.     

一种基于增强奇偶校验码级联极化码的新型编译码方法

极化码作为一种纠错码,具有较好的编译码性能,已成为5G短码控制信道的标准编码方案。但在码长较短时,其性能不够优异。提出一种基于增强奇偶校验码级联极化码的新型编译码方法,在原有的奇偶校验位后设立增强校验位,对校验方程中信道可靠度较低的信息位进行双重校验,辅助奇偶校验码在译码过程中对路径进行修剪,以此提高路径选择的可靠性。仿真结果表明,在相同信道、相同码率码长下,本文提出的新型编译码方法比循环冗余校验(cyclic redundancy check,CRC)码级联极化码、奇偶校验(parity check,PC)码级联极化码误码性能更优异。在高斯信道下,当码长为128、码率为1/2、误码率为10-3时,本文提出的基于增强PC码级联的极化码比PC码级联的极化码获得了约0.3 dB增益,与CRC辅助的极化码相比获得了约0.4 dB增益。     

A polymer transistor circuit using PDHTT

A digital circuit using polymer thin-film transistors on polyester substrate is presented. The circuit consists of 171 transistors and converts a parallel word of four bits into a serial bit sequence by use of gates and flip-flops with level shifters. The integrated clock generator runs at oscillation frequencies of approximately 200 Hz with supply voltages of -25 V/+12 V. The polymer poly(3,3'-dihexyl-2,2':5',2'-terthiophene) (PDHTT) is used as semiconducting material. Measurement results for the circuit demonstrate that PDHTT can be used for digital polymer circuits.     

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended+reference current-mode signaling with three dc references for maximum bandwidth per pin. A test chip with six I/O pins was fabricated in 0.35-μm CMOS and tested in a 28-Ω evaluation system using on-chip 2¹⁰ pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices     

On beamforming with finite rate feedback in multiple-antenna systems

We study a multiple-antenna system where the transmitter is equipped with quantized information about instantaneous channel realizations. Assuming that the transmitter uses the quantized information for beamforming, we derive a universal lower bound on the outage probability for any finite set of beamformers. The universal lower bound provides a concise characterization of the gain with each additional bit of feedback information regarding the channel. Using the bound, it is shown that finite information systems approach the perfect information case as (t-1)2/sup -B/t-1/, where B is the number of feedback bits and t is the number of transmit antennas. The geometrical bounding technique, used in the proof of the lower bound, also leads to a design criterion for good beamformers, whose outage performance approaches the lower bound. The design criterion minimizes the maximum inner product between any two beamforming vectors in the beamformer codebook, and is equivalent to the problem of designing unitary space-time codes under certain conditions. Finally, we show that good beamformers are good packings of two-dimensional subspaces in a 2t-dimensional real Grassmannian manifold with chordal distance as the metric.     

Parity generator circuit using a multistate resonant tunnellingbipolar transistor

A four-bit parity generator circuit using a single resonant tunnelling bipolar transistor (RTBT) exhibiting two negative transconductance regions in the characteristics, is demonstrated. The circuit uses only one transistor as compared to 24 needed in conventional logic. The present circuit also provides significant advantages over previous parity generator circuits using resonant tunnelling diodes. The same circuit, when used with only two input bits, will act as an exclusive-NOR gate     

Determination of best shortened linear codes

The quality of a block code is determined by its capability to protect data against undetectable errors and by the number of check bits that are required for that purpose. For a given number of check bits there are codes with optimum bit error detecting capability in shortened block lengths. These codes are determined and tabulated. The residual error characteristics of some of the tabulated codes are compared with those specified in ISO/CCITT or IEC standard data transmission protocols. For block lengths and bit error rates that are typical in process control applications, the residual error rate of the determined codes is more than six orders of magnitude smaller than that of codes specified by widely used standard transmission protocols     

Novel Analog Calibration Technique for Current-Steering DACs’ Dynamic Performance

This paper reports the post-layout dynamic performance of a novel calibration technique for current-steering digital-to-analog converter that was proposed previously. This technique not only improves the linearity, but it does so with low power as well as a very low area. It uses an analog feedback loop consisting of four transistors to calibrate each bit of the DAC, and the same feedback circuit is used for all the bits, thus significantly saving the chip area. Layout of the 10-bit calibrated CS DAC circuit was done in a 180-nm technology; the total area of the DAC and the calibration circuit together was 0.16 \(\hbox {mm}^{2}\). Simulation results show that the spurious free dynamic range is 62 dB for signals of 1 MHz at a sampling frequency of 100 MS/s.     

Generation of random bits with accurate and reproducible statistical properties

The generation of "accurate" random bits is the key problem of the techniques which use random numbers. First the author establishes the accuracy requirements of a random bit generator for serial and parallel number generation. Then known methods are shown to be unsatisfactory for accurate applications. An accurate bit generator is proposed which provides a binary variable with equiprobable values within a 10^-4to 10^-5accuracy range.     

All-optical address extraction for optical routing

This paper describes the optical circuit that enables to extract address from a transmitted cell in an all-optical manner. Nonlinear optical loop mirrors (NOLM's) are used as all-optical switches in order to confirm the operation of the proposed circuit. The control pulses synchronized with address bits are generated from the transmitted cell. The address bits are successfully extracted without any electronic control circuit. The factors that limit an attainable bit rate are discussed. If we use NOLM composed of a 2-km-long fiber, 110 Gb/s is attainable for the 4 ps FWHM input pulse with RZ format